JPS5827247A - Logical device - Google Patents

Abstract

PURPOSE:To check whether data is transferred normally or not by logically processing the output of a J-K flip-flop to be controlled by a register controlling signal. CONSTITUTION:Input data 11 is held in a register 1 and an output of the register 1 is processed by a logical circuit 3 and inputted to a register 2. An output signal 18 of a J-K flip-flop 5 is changed at its value in every setting of the register 1. An output signal 19 of a J-K flip-flop 6 is inverted in every setting of the register 2. The outputs of the J-K flip-flops 5, 6 are inputted to a comparator 7, which finds an exclusive OR between these inputs. If control signals 16, 17 are not outputted by any fault, an output signal of a comparator 7 is kept at logic ''1''.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic device, and more particularly to a synchronous logic device capable of detecting all malfunctions of control signals during transfer of data, etc. between registers.

As an example of a conventional synchronous logic circuit is shown in FIG. It is composed of a circuit 3, a second register 2 that holds the output result of the logic circuit 3, and a control circuit 4 that controls the settings of the first register 1 and the second register 2.

FIG. 2 is a waveform diagram of signals in each part of the logic device shown in FIG. 1.

The operation of the logic device shown in FIG. 1 will be explained using FIG. 2.

FIG. 2 shows that the operation is performed at the falling edge of the clock signal 14, and the first register l and the second register 2 have control signals 16 and 17 at a high level value (logic 1111+
), and a low level value (logic ``01'') indicates that information is to be retained.

Input information from the input signal 11 is stored in the first register 1. The output 12 of the first register 1 is input to the logic circuit 3, and the processing result 12'' is stored in the second register 2 and transferred to the next stage as output data 13.At this time, the first register 1 Instead of storing data in the register 2 of No. 2 every clock, as shown in FIG. A control method is often used in which the data 11 and 12' are input only when the data is stored, and the data is held in the first register 1 and the second register 2 at other times. This is because in the event of a failure, the information remains in the register, making it easy to analyze, or because long-term data longer than the clock cycle is required, such as data written to a memory element using a MOS-IC. However, if the control signal 16 or 17 is not output due to a failure, the previously held information is output to the first register 1 or second register 2 and the information is transferred to the next stage. In this case, error detection using codes such as parity has the disadvantage that errors cannot be detected and are erroneously processed without knowing that a failure has occurred.

An object of the present invention is to provide a logic device that detects the manual state of a control signal and prevents malfunction by having a flip-flop in J- that is inverted by the register control signal of each stage.

The logic device of the present invention includes a first register that holds information of logic 1°l'' or "0", a logic circuit that calculates the output of the first register, and an output signal of the logic circuit that is converted into a human input signal. In the logic device in which the signal information is changed, a first J- flip-flop whose output information is inverted by the first register control signal, and a second flip-flop whose output information is inverted by the second register control signal are provided. J- includes a flip-flop and a comparison circuit for determining whether the first and second flip-flops are correctly inverted.

Next, embodiments of the present invention will be described using the drawings.

FIG. 3 is a block diagram of one embodiment of the present invention.

The logic device of this embodiment includes a first register 1 that holds an input signal 11, a logic circuit 3 that calculates the output of the first register l, and a register 2 that holds the calculation result of the logic circuit 3.
, a control circuit 4 that holds and controls the first register 1 and the second register 2, and a flip-flop 5 connected to the first J-, which receives all inputs of a signal 16 that controls the holding of the first register 1. , a flip-flop 6 for the second J- which inputs the signal 17 that controls the holding of the second register 2, and a comparison circuit 7 for comparing the outputs of the flip-flops for the first and second J-. be done.

Figure 1 and Figure 3? As is clear from the comparison, the logic device of the present invention is different from the conventional logic F! The difference from the conventional device is that two flip-flops and a comparison circuit are added to the device, and a function is provided to check that the control signals 16 and 17 of each register are correctly output.

FIG. 4 is a waveform diagram of signals at various parts of the embodiment shown in FIG. 3.

The operation of the embodiment shown in FIG. 3 will be explained using the fourth figure.

Input data 11 is held in first register 1 by control signal 16 generated by control circuit 4 in response to trigger signal 15 . The held output 12 of the first register l is processed by the logic circuit 3 and sent as a signal 12' to the register 2V of the next stage.
c. Input. Here, a control signal 17 generated by the control circuit 4 is input, information 12' is set in the second register 2, and is sent as an output signal 13 to the next stage. Here, the first
A control signal 16 for controlling the seratra of the first register 1 is input to the J- terminal of the flip-flop 5 and the terminal J- of the flip-flop 5. Therefore, when the first register 1 is set, both the J terminal and the terminal become logic 11'', and the output signal 18 is inverted, but the value of the output 18 does not change at any other time.
The output signal 18 is inverted every time the control signal 16 is output, that is, the first register 1 is connected to the row J terminal and the second register 2 is set. . The output signals 18 and 19 are the comparator circuit 7.
The exclusive OR is performed and the signal 2Of6 is output. Here, in the initial setting, the output signals 18 and 19 of the two J- flip-flops 5 and 6 are set to the same value. Therefore, after the control signals 16 and 17 are output to the j-circle, the values of the output signals 18 and 19 are both inverted and become the same value. Therefore, after the control signal 17 is output, the output 20 of the comparator circuit 7 always becomes logic "0".

Now, if the control signal 16 fails for some reason and is not output, the first J- is connected to the flip-flop 5.
The output 18 of the second
Since the output 19 of the flip-flop 6 is inverted at J-, the subsequent output signal 20 of the comparator circuit 7 is logic +1111
A malfunction has occurred. Further, when the control signal 17 is not output due to a failure, the output signal 18 of the flip-flop 5 is inverted to the first J-, but the output signal 18 of the flip-flop 5 is inverted to the first J-.
Since the output signal 19 of the flip-flop 6 is not inverted, the subsequent output signal 20 of the comparator circuit 7 is no longer the same.
1'', indicating that a failure has occurred.

Further, it is possible to distinguish whether the control signal 16 or the control signal 17 has failed by looking at (iii) of the output signal 20 during the time between the output of the control signals 16 and 17. In this way, it is possible to detect whether the control signals of each stage are normally output and the data information is transferred correctly.

As explained above, the present invention includes a flip-flop in J- controlled by a register control signal in the previous stage and a flip-flop in J- controlled by a register control signal in the next stage.
By adding a comparison circuit for comparing these outputs, it is possible to check whether the information is being transferred normally.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a conventional logic circuit, FIG. 2 is a waveform diagram of signals in each part of the logic circuit shown in FIG. 1, and FIG. 3 is a block diagram of an embodiment of the present invention. FIG. 4 is a waveform diagram of signals at each part of the embodiment shown in FIG. 3. 1...--First register, 2...--Second register, 3...-Logic circuit, 4...--Control device, 5...- Flip-flop on the first J-,
6... Flip-flop to the second J-, 7...
... Comparison circuit, 11... Input data, 12
．． 12', 13... Output data, 14...
...Clock signal, 15...Trigger signal, 16
゜17... Control signal, 18, 19.20...
...Output signal. 9-) Mustard 1 Sodium 2 fig.

Claims (1)

[Claims] A first register that holds information of logic 1111 or l1OL, a logic circuit that operates on the output of the first register, and a second register that uses the output signal of the logic circuit as an input signal and holds the signal information. and a comparison circuit for determining whether or not the output information is inverted in accordance with the control signal of the second register; A logical device characterized by.