JPH06175888A - Abnormal access detection circuit - Google Patents

Abstract

PURPOSE:To reduce cost by shortening a term required for developing and design a system to easily make an abnormal access detection circuit to cope with correspond to a change of an address area by detecting at the time of access abnormality to the specific address having a fear with the normal operations not guaranteed in a microcomputer system. CONSTITUTION:The system using a microcomputer is provided with an address decoder circuit 5 to input the specific address from an address bus 1 and at the same time to assert an abnormality detecting address setting signal WS when a prescribed control signal is inputted from a control bus 3, and abnormal address detecting circuit 6 set data imparted on a data bus 2 as an abnormality detecting address when the abnormality detecting address setting signal is asserted and thereafter to detect the time when the address on the address bus 1 is coincident with the abnormality detecting address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system using a microcomputer, and more particularly to an abnormal access detection circuit having a function of detecting and handling an abnormal access.

[0002]

2. Description of the Related Art Generally, in a system using a microcomputer (hereinafter referred to as a microcomputer system), there is a possibility that a program may run out of control due to access to a specific address, or an address that is unnatural in operation may be used. There is provided hardware for detecting an abnormal access such as a case where an access occurs and for prohibiting subsequent operations and performing exception processing.

FIG. 12 shows a conventional access abnormality detecting circuit, in which an abnormal address to be detected is set in the address decoder circuit 100, the address decoder circuit 100 detects the access time of the abnormal address, and an error flag is detected. Is configured to generate.

However, such a hardware measure requires redesign of the address decoder circuit 100 when the address area is changed, and in some cases, the design of the entire circuit needs to be reviewed. .

Therefore, as a software measure, it is conceivable to detect the above-mentioned address by software and perform prohibition processing or interrupt processing, but the number of steps of the program accompanying this is enormous.

[0006]

As described above, in the conventional microcomputer system, the circuit for detecting and coping with the abnormal access to a specific address, which may not guarantee the normal operation, changes the address area. There was a problem that could not be easily dealt with.

The present invention has been made to solve the above problems, and a circuit for detecting and coping with an abnormal access to a specific address, which may prevent normal operation, can be easily changed in the address area. It is an object of the present invention to provide an abnormal access detection circuit that can deal with the above.

[0008]

According to the present invention, in a system using a microcomputer, data provided on an address setting bus or a data bus when an abnormality detection address setting signal is asserted is used as an abnormality detection address. A register circuit to be set and a comparison detection circuit for comparing whether or not an address on the address bus matches an abnormality detection address set in the register circuit and generating an error flag at the time of matching judgment are provided. Characterize.

[0009]

By setting the detection address in the register circuit for setting the abnormality detection address via the address setting bus or the data bus, it is possible to detect an abnormal access to a specific address that may not guarantee normal operation. By using the detection output, it becomes possible to take measures such as prohibiting the subsequent operation or performing exception processing. As a result, when changing the address area to be detected,
Redesign of the address decoder circuit etc. is not required, and the change design of the microcomputer system becomes easy.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. 1 to 3 show a plurality of specific examples of a part of a microcomputer system according to an embodiment of the present invention.

In the microcomputer system shown in FIG. 1, 1
Is an address bus (for example, 8 bits), 2 is a data bus (for example, 8 bits), 3 is a control signal bus, 4 is a CPU (central processing unit) connected to each bus, 5 is an address decoder circuit, and 6 is An abnormal address detection circuit, 7 is an address setting bus, and 8 is a control signal line.

The abnormal address detection circuit 6 is connected to the address bus 1 and the address setting bus 7 and is supplied to the address setting bus 7 when the abnormality detection address setting signal WS is asserted. The register circuit that sets data as an abnormality detection address is compared with whether or not the address on the address bus 2 subsequently matches the abnormality detection address set in the register circuit, and the error flag EF is set at the time of determination of a match. And a comparison and detection circuit for generating.

According to the above configuration, the address setting bus 7
By setting the detection address of the abnormal address detection circuit 6 via the, the abnormal operation of the access to the specific address that may not guarantee the normal operation is detected, and the detection output is used to prohibit the subsequent operation or to make an exception. It becomes possible to deal with the processing. This eliminates the need to redesign the address decoder circuit 5 when changing the address area, and facilitates the change design of the microcomputer system.

If the abnormal address detection circuit 6 is provided on the same semiconductor chip as the CPU 4,
The cost increase due to the addition of the abnormal address detection circuit can be almost ignored.

The microcomputer system shown in FIG. 2 is different from the microcomputer system shown in FIG. 1 in that when the abnormality detection address setting signal WS is asserted, the data provided on the data bus 2 is used as an abnormality detection address. The difference is that it is set in the address detection circuit 6, and the other parts are the same, so the same reference numerals as in FIG.

This microcomputer system basically performs the same operation as the microcomputer system shown in FIG.
The address setting bus (7 in FIG. 1) for setting the abnormality detection address is not required.

The microcomputer system shown in FIG. 3 is different from the microcomputer system shown in FIG. 1 in that the abnormality detection address setting signal WS is asserted by the address decoder circuit 5, and the other points are the same, so that the microcomputer system in FIG. The same reference numerals are given.

That is, the address decoder circuit 5 is connected to the address bus 1 and the control bus 3,
The abnormality detection address setting signal WS is asserted when a specific address is input from the address bus 1 and a predetermined control signal is input from the control bus 3.

According to the above configuration, the abnormal address detection circuit 6 is provided via the address bus 1, the data bus 2 and the control bus 3.
By changing and setting the detection address of, detect the abnormal access to the specific address that may not guarantee the normal operation, and use the detection output to prohibit the subsequent operation or take exception processing. It will be possible. This eliminates the need to redesign the address decoder circuit 5 when changing the address area, and facilitates the change design of the microcomputer system.

Further, by setting the abnormal address detection area in the program, it is possible to change the address area in the middle of the program, and the degree of freedom of the microcomputer system is improved. 4 to 11 are circuit diagrams showing a plurality of specific examples of the abnormal address detection circuit 6.

In the abnormal address detection circuit shown in FIG.
The eight latch circuits 71 to 78 form a register circuit, an address given on the data bus 2 is given as a data input, and the abnormality detection address setting signal WS is inputted as a latch control signal. . Thus, when the abnormality detection address setting signal WS is asserted, the data provided on the data bus 2 is latched as the abnormality detection address data.

The eight exclusive NOR circuits 81 to 88, the two 4-input AND circuits 91 and 92, and the one 2-input AND circuit 93 form a comparison detection circuit. The addresses on the address bus 2 and the latch outputs (abnormality detection address data) of the latch circuits 71 to 78 are input to the exclusive NOR circuits 81 to 88.

The outputs of the four exclusive NOR circuits 81 to 84 are input to one of the four-input AND circuit 91 and the other four-input AND circuit 91 is input.
The outputs of the remaining four exclusive NOR circuits 85 to 88 are input to the input AND circuit 92. 2-input AND circuit 93
The outputs of the two four-input AND circuits 91 and 92 are input to. Thereby, it is compared whether or not the address data on the address bus 1 matches the abnormality detection address, and an error flag EF is generated at the time of matching judgment.

The abnormal address detection circuit shown in FIG.
Compared to the abnormal address detection circuit shown in FIG. 2, the 2-input AND circuit 93 of the comparison detection circuit is changed to a 3-input AND circuit 94, and the read cycle designating signal R is used as one input.
Since the point that EAD is given is different and the others are the same, the same reference numerals as in FIG. 4 are given.

The operation of this abnormal address detection circuit is shown in FIG.
The operation is basically the same as the operation of the abnormal address detection circuit shown in, except that the error flag EF is generated only when the abnormal address is detected in the data read cycle.

The abnormal address detection circuit shown in FIG.
The read cycle designating signal is changed to the write cycle designating signal WRITE as compared with the abnormal address detecting circuit shown in FIG. 5, and the same parts as those in FIG. The operation of the abnormal address detection circuit is characterized in that the error flag EF is generated only when the abnormal address is detected in the data write cycle.

The abnormal address detection circuit shown in FIG.
Compared with the abnormal address detection circuit shown in FIG.
1a to 78a are provided with a reset terminal CL, and a reset signal RESET is applied to each reset terminal CL in common at a predetermined timing. .

The operation of this abnormal address detection circuit is shown in FIG.
Although the operation is basically the same as the operation of the abnormal address detection circuit shown in, the initial value of each bit of the abnormal detection address is set to "0" by the reset signal RESET (at address 0). It is characterized in that it is set).

The abnormal address detection circuit shown in FIG.
Compared with the abnormal address detection circuit shown in FIG.
1b to 78b are provided with a preset terminal PR, the reset signal RESET is commonly given to each preset terminal PR at a predetermined timing, and the other points are the same, and therefore, the same reference numerals as those in FIG. 4 are given. .

The operation of this abnormal address detection circuit is shown in FIG.
Although the operation is basically the same as the operation of the abnormal address detection circuit shown in, the initial value of each bit of the abnormal detection address is set to "1" by the reset signal RESET (maximum address). Is set)) is characteristic.

The abnormal address detection circuit shown in FIG.
Compared with the abnormal address detection circuit shown in FIG. 1, the latch circuits 71a, 73a, 75a, 77a with reset terminals and the latch circuits 72b, 74b, 76 with preset terminals are provided.
b and 78b are used, and the reset signal RES is commonly used for each reset terminal and the preset terminal at a predetermined timing.
The difference is that ET is given, and the others are the same, so the same reference numerals as in FIG. 4 are given.

The operation of this abnormal address detection circuit is characterized in that the initial value of each bit of the abnormal detection address is set to a specific value (set to a specific address) by being supplied with a reset signal and a preset signal. There is.

The abnormal address detection circuit shown in FIG. 10 has four inputs compared with the abnormal address detection circuit shown in FIG. 4, for example, in the abnormal address detection circuit shown in FIG. The AND circuit 92 is modified so that the inputs other than the fourth bit input are fixed to the "1" level inputs (connected to the "1" level nodes), and the same portions as those in FIG. 5 are the same. The code is attached.

The operation of this abnormal address detection circuit is performed regardless of the value of the lower several bits of the address by the comparison detection circuit.
It is characterized in that an abnormal address is detected in a certain address area determined by the upper bits of the address.

The abnormal address detecting circuit shown in FIG. 11 is different from the abnormal address detecting circuit shown in FIG. 5 or 6 in that the read cycle designating signal or the write cycle designating signal is changed to a flag control signal FLAGCTRL. The same parts as those in FIG. 5 are designated by the same reference numerals.

The operation of this abnormal address detection circuit is characterized in that the error flag EF can be controlled by the flag control signal FLAGCTRL. For example, the flag control signal FLAGCTRL is set when the address to be detected as an abnormality is not set, or when the function of the circuit of the present invention is to be disabled in the microcomputer system.
The generation of the error flag EF can be prohibited by deactivating the flag.

The present invention is not limited to the above-mentioned embodiment but is generally applicable to a microcomputer system, for example, a node of a local area network (LAN) used for communication inside a car. It is also applicable to a control device (LAN controller) connected to the.

[0038]

As described above, according to the abnormal access detection circuit of the present invention, a circuit for detecting and handling an abnormal access to a specific address, which may cause a failure in normal operation, is provided for changing the address area. It becomes possible to deal with it easily. Therefore, the development and design period of the system using the microcomputer can be shortened, and the cost of the system can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an abnormal access detection circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a modified example of the abnormal access detection circuit of FIG.

FIG. 3 is a block diagram showing another modification of the abnormal access detection circuit of FIG.

FIG. 4 is a circuit diagram showing a specific example of an abnormal address detection circuit in FIG.

5 is a circuit diagram showing another specific example of the abnormal address detection circuit in FIG.

6 is a circuit diagram showing still another specific example of the abnormal address detection circuit in FIG.

7 is a circuit diagram showing still another specific example of the abnormal address detection circuit in FIG.

8 is a circuit diagram showing still another specific example of the abnormal address detection circuit in FIG.

9 is a circuit diagram showing still another specific example of the abnormal address detection circuit in FIG.

10 is a circuit diagram showing still another specific example of the abnormal address detection circuit in FIG.

FIG. 11 is a circuit diagram showing still another specific example of the abnormal address detection circuit in FIG.

FIG. 12 is a block diagram showing an abnormal access detection circuit used in a conventional microcomputer system.

[Explanation of symbols]

1 ... Address bus, 2 ... Data bus, 3 ... Control signal bus, 4 ... CPU, 5 ... Address decoder circuit, 6 ... Abnormal address detection circuit, 7 ... Address setting bus, 71 to 7
8 ... Latch circuit, 71a-78a ... Latch circuit with reset terminal, 71b-78b ... Latch circuit with preset terminal, 81-88 ... Exclusive NOR circuit, 91, 92 ... 4-input AND circuit, 93 ... 2-input AND circuit, 94 ... 3-input AND circuit.

Claims (2)

[Claims] 1. In a system using a microcomputer, a register circuit for setting data provided on an address setting bus or a data bus as an abnormality detection address when an abnormality detection address setting signal is asserted, and an address bus. Compare whether the above address matches the error detection address set in the register circuit above,
An abnormal access detection circuit, comprising: a comparison detection circuit that generates an error flag when a match is determined. 2. The abnormal access detection circuit according to claim 1, further comprising an address decoder which asserts an abnormality detection address setting signal when a specific address is input from the address bus and a predetermined control signal is input from the control bus. A circuit is provided, wherein the register circuit sets an address given on the data bus as an error detection address when the error detection address setting signal of the address decoder circuit is asserted. Access detection circuit.