JPH02190938A - Parity check device - Google Patents

Abstract

PURPOSE:To secure the margin of check timing by providing the device with a latch part, a generation part and a check part. CONSTITUTION:The latch part 43 inputs a latch clock, data and a control signal and latches the data and the control signal in the period of the latch clock and the generation part 41 counts up the number of logic '1' in data outputted from the latch part 43, and forms and outputs check data indicating that the counted value is an even or odd number. The check part 42 inputs the control signal and the check data outputted from the latch part 43, and when the latched control signal is active, decides the check data by using the inactive state of the latched control signal as a trigger and outputs the decided result. Namely even when the control signal inputted to the latch part 43 is turned to the inactive state, the control signal inputted to the check part 42 is not turned to the inactive state until the succeeding latch. Consequently, the margin of the check timing at the time of parity check can be secured corresponding to the acceleration or the like of a system.

Description

[Detailed Description of the Invention] [Summary] Regarding a parity check device suitable for securing a check timing margin during a parity check, the present invention is designed to ensure a check timing margin during a parity check in response to increased system speed. and has a latch section, a generation section, and a check section, with the aim of preventing a decrease in reliability.
The latch section inputs the latch clock, data, and control signal, and latches the data and control signal every cycle of the latch clock.The generator section inputs the data output from the latch section. The checking section counts the number of logic "l"s in the data and generates and outputs checking data indicating whether the number is even or odd. The control signal output from
It is configured to determine errors and output the results.

[Industrial application field]

The present invention relates to a parity check device for detecting the presence or absence of an error in a binary code in a computer system, and more particularly to a parity check device suitable for securing a check timing margin during a parity check.

In recent years, with the demand for high reliability in computer systems, there has been a demand for adding a parity bit to each data unit stored in a storage device to detect the presence or absence of data errors. Various parity check methods have been provided for this purpose, but as computer systems become faster, it has become necessary to ensure a check timing margin during parity checks.

[Conventional technology]

FIG. 4 is a block diagram showing an example of a computer system in which a parity check device is configured. In the figure, 1 is a central processing unit (CPU), 2 is a main memory,
3 is a parity generation device, 4 is a parity check device, 5
1 is an interrupt control device, 6 is a read/write (R/W) control signal, 7 is a data bus, 8 is a parity signal, 9 is an address bus, and 10 is an oscillator. Note that although computer systems generally include input/output devices, they are omitted for the sake of brevity.

In the above configuration, when data is written to the main storage device 2 by the CPU, the data is checked in the parity generation device 3. For example, in the case of an even parity check, the focus is set to logic "1". A 1-bit value is generated so that the number of bits is an even number, is added to the write data as a parity bit, and is stored in the main memory 2.
Writing is performed. On the other hand, when data is read from the main memory device 2, the parity check device 4 checks the read data and the parity bit to see if the number of bits that are logical "1" is an even number. If the number is odd, it is determined as an error and the NMT interrupt, which is an emergency interrupt, is sent to C through the interrupt control device 5.
Generate in PU1.

FIG. 5 is a block diagram of a conventional parity check device 4. In the figure, 41 is a generating section;
42 is a checking unit, and the generating unit 41 inputs the data and parity bits read from the main storage device 2, counts the number of bits that are logical “L”, and determines that the counted number is an even number. It generates and outputs check data consisting of 1 bit indicating whether the number is an odd number or not.

The check unit 42 receives the read control signal 6 from the CPU I.
The check data is inputted, the check data is determined whether it is correct or incorrect, and the result is output to the interrupt control device 5.

FIG. 6 is a time chart of the conventional parity check device 4 mentioned above. As shown in the figure, the read control signal 6
By becoming active (Low), data and a parity bit are output from the main storage device 2, and check data is generated in the generation unit 41 using the data. When the checking section 42 detects a change in the control signal 6 to inactive, it determines whether the check data is correct or incorrect and outputs the result.

[Problem to be solved by the invention]

However, with the above conventional technology, when the clock rate etc. of a computer system is increased to speed it up, or in a different system, the read cycle becomes shorter and the timing at which the control signal changes to inactive becomes earlier. ing. In such a case,
Since the judgment in the check section is accelerated and a margin for data generation in the generation section cannot be secured, there is a problem in that the parity check is not performed properly and malfunction occurs.

The present invention was created in view of these problems, and
It is an object of the present invention to provide a parity check device that prevents deterioration of reliability by ensuring a check timing margin during parity check in response to speeding up of the system.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention. In the figure, parts that are the same as the conventional ones are given the same reference numerals.

As shown in FIG.
The latch unit 43 inputs the latch clock, data, and control signal (No. 3), and latches the data and control signals every cycle of the latch clock. 41 is the latch portion 43
Input the data output from “
1'' and generates and outputs checking data indicating whether the number is even or odd, and the checking section 42 receives the control signal output from the latch section 43. and input the check data, and check whether the check data is correct or not according to the timing of the control signal.
A parity check device is characterized in that it determines errors and outputs the results.

[Effect]

In the present invention, the latch section 43 latches the logic states of data and control signals once every cycle of the latch clock,
The latched data is inputted to the generating section 41, and the control signal is inputted to the checking section 42. When the latched control signal is active, the checking unit 42 triggers when the latched control signal becomes inactive with respect to the check data to be determined generated by the generating unit 41. Make a judgment using
Output the result. As a result, data and control signals are latched in the latch unit 43, and immediately after the generation unit 41 starts generating check data to be determined, the control signal input to the latch unit 43 becomes inactive. Even if it becomes, the control signal input to the check unit 42 does not become inactive until the next latch, so that a sufficient amount of time can be obtained for the generation unit 41 to confirm its generation.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of a parity check device that is an embodiment of the present invention. The parity check device shown in the same figure is configured in the computer system shown in FIG. 4. Components that are the same as the conventional configuration shown in FIG. Omitted. In the figure, a generating section 41 and a checking section 42 operate in the same manner as conventional ones. 43a is a data D-FF,
43b is D-FF for parity, 43c is D-FF for control signal.
-F F, and the latch clock a generated by the oscillator 1o is input to each of them. D-F for data
F43a is configured with the same number of D flip-flops as the data lines of the data bus 7, and each data line is connected as input data. It latches data using the latch clock a and outputs the latched data signal. It is sent to the generating section 41. D-FF43b for parity
The D flip-flop is configured with one D flip-flop to which the parity signal 8 is connected as input data, which is latched by the latch clock a and sends the latched parity signal C to the generator section 41.

The control signal D-FF 43c is configured with one D flip-flop, and is connected to the control signal 6 from the CPU 1 as input data.The control signal D-FF 43c is latched by the latch clock a, and the latched control signal d is checked by a section. 42. The generator section 41 receives the latched data signal and the latched parity signal C, generates check data C, and sends it to the check section 42 . The check section 42 uses the change of the input latched control signal d from active to inactive as a trigger to determine whether the input check data e is correct or incorrect, and sends the resulting signal r to the interrupt control device n. Send to 5.

FIG. 3 is a time chart in the above configuration. As shown in the figure, when the read control signal 6 from the CPUI becomes active (Low) (■), read data is output from the main memory device 2 to the data bus 7 and the parity signal line 8 (■), The data and control signals are sent to the data D-
FF43a, parity D-FF43b, control D-F
The latched data signal b, parity signal C, and control signal d are latched by each of F43C and output to the latch (B) by the next rising edge (■).

■), this latched data signal and parity signal C
As a result, data for CHI/R is generated in the generator 41 (■).Then, by the next rising edge of the latch clock a (■B), the control signal 6 input to the control D-FF 43C is input. When the control signal d becomes active, the control signal d input to the check unit 42 becomes inactive by the latch at the next rising edge (■B''), and at this time, the check unit 42 checks whether the input check data is correct or incorrect. Make a judgment and output the result (■).

In this manner, in this embodiment, the time for generating the check data in the generator 41 can be secured within one cycle of the latch clock, regardless of the timing at which the control signal from the CPUI becomes inactive. Further, by changing the period of the latch crotter, it can be adjusted to correspond to the required time.

〔Effect of the invention〕

As explained above, according to the present invention, even when computer systems become faster, parity checks can be performed without error, and by adjusting the latching interval, it is compatible with systems with different read cycles, etc. This greatly contributes to improving the ε-axis properties of various computer systems.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a time chart in the embodiment, Fig. 4 is a block diagram of a computer system, and Fig. 5 is a block diagram of a conventional computer system. Block diagram of parity check device, No. 6
The figure is a time chart in FIG. 4; Parity check device; 6; Control signal; 7: Data bus; 8; Parity signal; 41i digital circuit; 42; Check unit; 43; Latch unit; 43a; D-FF for data; -FF, 43C; D-FF for control signal, a; latch clock.

Claims (1)

[Claims] It has a latch section (43), a generation section (41), and a check section (42), and the latch section (43) receives a latch clock, data, and a control signal. The generator section (41) receives the data output from the latch section (43), and latches the data and control signals every cycle of the latch clock.
The checking section (42) counts the number of , and generates and outputs checking data indicating whether the number is even or odd. A parity check device, characterized in that it inputs a control signal and the check data, determines whether the check data is correct or incorrect based on the timing of the control signal, and outputs the result.