JP3036442B2 - Memory monitoring method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory monitoring method, and more particularly to a method for detecting and correcting a bit error when writing data.

[0002]

2. Description of the Related Art Conventionally, as described in JP-A-59-175100, after data is written to a memory, a parity check is performed when the data is read and an error is notified if there is an error. Thus, the reliability of the data was improved. However, in this method, even if a value is wrong due to a memory failure when data is written to the memory, no error can be found until the value is read and a parity check is performed. Therefore, in the conventional memory monitoring method, a method of reading data in a pseudo manner when writing data to the memory, performing a parity check of the data, and rewriting the data when an error is found is used. Have been.

FIG. 9 is a block diagram of a conventional memory monitoring system as described above.

[0004] This conventional memory monitoring system employs a CPU 91
, Main memory 2 and dummy read signal generation unit 93
, An address holding unit 94, a parity generation / check unit 5, and a parity memory 6.

The CPU 91 activates the memory write signal 13 at the time of data writing, outputs data to be written to the data bus 11, and specifies the address of the data to be written via the address bus 12. When reading data, the memory read signal 14 is activated,
An address to be read is output to the address bus 11.

The main memory 2 has a memory write signal 13
Is input, the data on the data bus 11 is transferred to the address bus 1
When the data is stored at the address indicated by 2 and the memory read signal 14 is input, the data stored at the address indicated by the address bus 12 is output to the data bus 11.

When the memory write signal 13 becomes active, the parity generation / check unit 5 generates a parity bit for the data on the data bus 11 and outputs it as parity data 28. When the memory read signal 14 becomes active, the parity data 28 is read from the parity memory 6, it is checked whether the parity data 28 corresponds to the data on the data bus 11, and the result is output as a parity result signal 27.

The parity memory 6 stores the memory write signal 1
When 3 is active, the parity data 28 from the parity generation / check unit 5 is stored at the address indicated by the address bus 11, and when the memory read signal 14 is active, the parity data stored at the address indicated by the address bus 11 is stored. 28 is output.

When the memory write signal 13 becomes active, the dummy read signal generator 93 outputs a dummy read signal 15 for reading data in a pseudo manner after a lapse of a predetermined time to the memory read signal 14.

The address holding unit 94 stores the address of the address bus 12 when the memory write signal 13 becomes active, and outputs the stored address to the address bus 12 when the dummy read signal 15 becomes active.

Next, the operation of the above conventional example will be described with reference to FIG.

FIG. 10 is a flowchart showing the operation of the memory monitoring system shown in FIG.

First, the CPU 91 outputs an address to be specified to the address bus 12 for writing to the memory, and outputs data to be written to the data bus 11. Then, the memory write signal 13 is activated. Since the memory write signal 13 has become active, the main memory 2 stores the data on the data bus 11 at the address specified by the address bus 12. Also, the memory write signal 13
Becomes active, the address holding unit 94 stores the address of the address bus 12, and the parity generation / check unit 5 generates the parity bit of the address of the address bus 12 and outputs it as the parity data 28. Then, the parity memory 6 stores the parity data 28 at the address specified by the address bus 12. (Step 1
11) When the data writing is completed, the dummy read signal generator 9
3 outputs the dummy read signal 15 to the memory read signal 14. The address holding unit 94 receives the dummy read signal 15
Becomes active, and outputs the stored address to the address bus 12. The main memory 2 receives a dummy read signal 15 input via the memory read signal 14.
Thus, the data stored at the address output from the address holding unit 94 to perform the data reading operation is output to the data bus 11. (Step 112) Since the dummy read signal 15 becomes active via the memory read signal 14, the parity memory 6
Outputs the parity bit stored at the address indicated by the address bus 12 as the parity data 28. The parity generation / check unit 5 performs a parity check to determine whether the data on the data bus 11 and the parity bit of the parity data 28 correspond to each other, and outputs the result to a parity result signal 27. (Step 113) When an error is detected by the parity check and an error is output to the parity result signal 27, the CPU 91 outputs an instruction to rewrite the data, and if no error is detected, ends the operation (Step 114).

[0014]

In the above-mentioned conventional memory monitoring method, if an error is found by a parity check by reading pseudo data, it takes a lot of time to rewrite the data. There was a problem.

An object of the present invention is to provide a memory monitoring method capable of rewriting data in a short time without imposing a load on software processing when an error is found in a parity check.

[0016]

In order to achieve the above object, a memory monitoring method according to the present invention provides a memory write signal which is activated when data is written, outputs data to be written to a data bus, and specifies an address of the data to be written. Performed by bus, and when reading data,
The memory read signal is activated, and the address to be read is output to the address bus.
CPU that stops operation while ait signal is active
When the memory write signal is input, the data on the data bus is stored at an address indicated by the address bus,
When the memory read signal is input, the main memory outputs data stored at the address indicated by the address bus to the data bus, and when the dummy read instruction signal becomes active, the data is read into the main memory in a pseudo manner. A dummy read signal for performing a write operation is output to the memory read signal, and when a dummy write instruction signal is activated, a dummy write signal for causing the main memory to perform pseudo data writing is output to the memory write signal. A dummy read / dummy write signal generating unit for storing an address of the address bus and data of the data bus when the memory write signal is active and the dummy write signal is not active;
When the dummy write signal is activated, the stored data and address are output to the data bus and the address bus, respectively, and when the dummy read signal is activated, the stored address is output to the address bus. And a data / address holding unit for outputting stored data as storage data, and comparing the data on the data bus with all the bits of the storage data when the dummy read signal becomes active, and checking if at least one bit differs, A data comparing unit that outputs an error to a signal, and stores parity data at an address indicated by the address bus when the memory write signal is active, and stores the parity data at an address indicated by the address bus when the memory read signal is active. A parity that outputs the data being read as the parity data. When the memory and the memory write signal are activated, a parity bit for the data on the data bus is generated and output as the parity data.When the memory read signal is activated, the parity data and the data on the data bus are output. And a parity generation / check unit for outputting the result as a parity result signal. When the memory write signal becomes active, the C / C is output after a predetermined time.
After activating the PUwait signal, a dummy read instruction signal is output, and if no error is detected by the parity result signal, the CPU wait signal is released and the CPU is returned to a normal operation, and an error is detected by the parity result signal. For example, after activating the dummy write instruction signal, the dummy read instruction signal is activated. If no error is detected by the check result signal, the CPU wait signal is released and the CPU is returned to a normal operation. If an error is detected, the dummy write instruction signal is activated again, and then the dummy read instruction signal is activated.This operation is repeated until no error is detected by the check result signal. If applicable, the data To stop the repetitive operation of the read re-write / to release the CPUwait signal the CP
U to return to normal operation, and a control unit for outputting an error signal to the CPU.

According to the present invention, after data is written from the CPU to the main memory, the dummy read / dummy write signal generator outputs a dummy read signal to temporarily read the written data, and the parity generator / checker checks the parity. When an error is detected, the data stored in the data / address holding unit is written into the main memory again, and the data is read out again. The bit is checked, and if an error is still detected, rewriting and checking of all bits are repeated a specified number of times.

Therefore, data rewriting is performed by hardware, not by software processing, so that data rewriting can be performed at high speed. In addition, since the check at the time of rewriting data checks all bits, the reliability of data can be improved as compared with the case of performing a parity check.

According to an embodiment of the present invention, the dummy read / dummy write signal generation unit receives and divides the frequency of the system clock and the system clock to generate a pulse signal having a cycle of one command signal. A first OR circuit that performs a logical sum operation of the dummy read instruction signal and the pulse signal to output the dummy read signal, and a logic of the dummy write instruction signal and the pulse signal. A second OR circuit that performs a sum operation and outputs the dummy write signal.

According to another embodiment of the present invention, the data / address holding unit performs an exclusive OR operation of the memory write signal and the dummy write signal and outputs an EX-OR signal as a memory instruction signal. A AND circuit that performs a logical product operation of the dummy write signal and the dummy read signal and outputs the result as an address output instruction signal;
When the memory instruction signal is input, the data of the data bus is stored, when the dummy write signal is input, the stored data is output to the data bus, and when the dummy read signal is input, the stored data is stored in the data bus. A data memory that outputs as storage data, and stores the address of the address bus when the memory instruction signal is input,
An address memory for receiving the address output signal and outputting the stored address to the address bus.

According to another embodiment of the present invention, the parity generation / check unit outputs the parity data as a parity input signal when the memory read signal is active; A second switch circuit that outputs a parity output signal as the parity data when a memory write signal is active;
A parity bit is output as the parity output signal such that the sum of the number of “1” bits included in the data of the data bus and the number of “1” bits included in the parity input signal is odd or even. It comprises a parity generation / check circuit, and a flip-flop which receives the parity output signal as input, receives the memory read signal as a clock input, and outputs the parity result signal.

Further, according to another embodiment of the present invention, the control unit is configured so that the counter value in the initial state is zero and the counter value stored when an error is output to the check result signal is one. And a counter section that outputs the counter value as a counter output if the counter value does not exceed a specified value.

According to another embodiment of the present invention, the data comparing section outputs a plurality of switch circuits for outputting each bit of the storage data as bit data when the dummy read signal is active; A plurality of EX-OR circuits for performing an exclusive OR operation on each bit data and each bit corresponding to the data on the data bus;
An OR circuit that performs a logical OR operation on the output of the OR circuit and outputs the result as the check result signal.

[0024]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a memory monitoring system according to an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a dummy read / dummy write signal generator 3 in FIG. 1, and FIG.
FIG. 4 is a block diagram of the parity generation / check unit 5 in FIG. 1, FIG. 5 is a block diagram of the control unit 7 in FIG. 1, and FIG. 6 is a data comparison unit 8 in FIG. FIG. The same numbers in FIG. 9 indicate the same components.

The memory monitoring method according to the present embodiment uses the CPU 1
, Main memory 2 and parity generation / check unit 5
, A parity memory 6, a dummy read / dummy write signal generation unit 3, a data / address holding unit 4, a data comparison unit 8, and a control unit 7.

The CPU 1 activates the memory write signal 13 when writing data, outputs data to be written to the data bus 11, and specifies the address of the data to be written via the address bus 12. When reading data, the memory read signal 14 is activated, and an address to be read is output to the address bus 11. When the CPU wait signal 26 is input, C
The operation stops while the PUwait signal 26 is active.

Dummy read / dummy write signal generator 3
When the dummy read instruction signal 21 becomes active,
A dummy read signal 15 for causing the main memory 2 to read data in a pseudo manner is output to the memory read signal 14, and when the dummy write instruction signal 22 becomes active, the data is written in the main memory 2 in a pseudo manner. The dummy write signal 16 for causing the memory write signal 1
Output to 3.

The data / address holding unit 4 stores the address of the address bus 12 and the data of the data bus 11 when the memory write signal 13 is active and the dummy write signal 16 is not active, and when the dummy write signal 16 becomes active. The stored data and the address are output to the data bus 11 and the address bus 12, respectively. When the dummy read signal 15 becomes active, the stored address is output to the address bus 12, and the stored data is output. Output as storage data 29.

The data comparing section 8 has a dummy read signal 15
Becomes active, the data on the data bus 11 is compared with all the bits of the storage data 29. If even one bit is different, an error is output to the check result signal.

The control unit 7 receives the memory write signal 1
6 becomes active, after a certain period of time, the CPUwai
After activating the t signal 26, the dummy read instruction signal 21 is activated. If no error is detected by the parity check result signal 27, the CPU w
The ait signal 26 is released to return the CPU 1 to the normal operation. If an error is detected, the dummy write instruction signal 22 is activated, and then the dummy read instruction signal 21 is activated. If no error is detected by the check result signal 30, the CPU wait signal 26 is released and the CPU 1 returns to the normal operation. If an error is detected, the dummy write instruction signal 22 is activated again, and then the dummy read instruction signal 21 is activated. This operation is repeated until no error is detected by the check result signal 30. If the number of times exceeds a certain number, the repeated operation of rewriting and rereading the data is stopped and the CPUwai is executed.
The t signal 26 is released to return the CPU 1 to the normal operation, and the error signal 23 is output to the CPU 1.

In this embodiment, the memory write signal 13,
The memory read signal 14, the dummy read signal 15, the dummy write signal 16, the dummy read instructing signal 21, and the dummy write instructing signal 22 are active low signals which become active at low output. The parity check signal 27 and the check result signal 30 are Low output signals indicating no error.

FIG. 2 is a block diagram showing the structure of the dummy read / dummy write signal generator 3 in FIG.

Dummy read / dummy write signal generator 3
Is a pulse generating circuit 31 which generates a pulse signal 35 having a cycle of one command signal by inputting and dividing the system clock 32 and the system clock 32
An OR circuit 33 that performs a logical sum operation of the dummy read instruction signal 21 and the pulse signal 35 and outputs the dummy read signal 15; a dummy write instruction signal 22 and the pulse signal 35
And an OR circuit 34 that performs a logical OR operation on the data and outputs the dummy write signal 16.

Dummy read / dummy write signal generator 3
Receives a dummy read instruction signal 21 and a dummy write instruction signal, and generates and outputs a dummy read signal 15 and a dummy write signal 16 having the same cycle as the pulse signal 35.

FIG. 3 is a block diagram showing the configuration of the data / address holding unit 4 in FIG.

The data / address holding unit 4 performs an exclusive OR operation of the memory write signal 13 and the dummy write signal 16 and outputs an EX-OR circuit 44 as a memory instruction signal 46, a dummy write signal 16 and a dummy read signal 1
5 and an AND circuit 43 for outputting an address output instruction signal 45 as an address output instruction signal 45. When the memory instruction signal 46 is input, the data on the data bus 11 is stored. When the dummy write signal 16 is input, the stored data is output. The data memory 41 outputs the data to the data bus 11 and outputs the stored data as the storage data 29 when the dummy read signal 15 is input, and stores the address of the address bus 12 when the memory instruction signal 46 is input and outputs the address output signal. 4
When 5 is input, the stored address is transferred to the address bus 1
2 and an address memory 42 that outputs the data to the address memory 2.

The data / address holding unit 4 stores the address of the address bus 12 and the data of the data bus 11 when the memory write signal 13 is active and the dummy write signal 16 is not active, and when the dummy write signal 16 becomes active. Data stored in the data bus 1
1, the stored address is output to the address bus 12, and when the dummy read signal 15 becomes active, the stored address is output to the address bus 12, and the stored data is output to the storage data 29.

FIG. 4 is a block diagram showing the configuration of the parity generation / check unit 5 in FIG.

The parity generating / checking unit 5 outputs a switch circuit 54 for outputting the parity data 28 as a parity input signal 56 when the memory read signal 14 is active.
And a switch circuit 53 that outputs the parity output signal 55 as the parity data 28 when the memory write signal 13 is active, and is included in the data of the data bus 11 ”.
1 “the number of bits and the number included in the parity input signal 56”
A parity generation / check circuit 51 that outputs a parity bit whose sum with the number of 1 ″ bits is odd or even as a parity output signal 55, and a parity output signal 5
5 as an input, a memory read signal 14 as a clock input, and a parity result signal 27 as a flip-flop 5
And 2.

At the time of data writing, the parity generation / check circuit 51 outputs a parity bit for the data on the data bus 11 as a parity output signal 55 and outputs it as the parity data 28 via the switch circuit 53.
At the time of data reading, the input parity data 28 is transmitted through the switch circuit 54 to the parity input signal 5.
6 is input to the parity generation / check circuit 51,
A parity check with the data on the data bus 11 is performed. The result of the parity check is output as a parity output signal 55 and output as a parity result signal 27 via the flip-flop 52.

FIG. 5 is a block diagram of the control section 7 in FIG.

The control unit 7 determines that the counter value in the initial state is zero, and when an error is output to the check result signal 30, adds 1 to the stored counter value, and if the counter value does not exceed the specified value. A counter 72 for outputting a counter value as a counter output 73;
It is composed of

The CONT 71 performs the same operation as the control unit 7 except that the number of errors of the check result signal 30 is detected by the counter output 73.

The number of errors sent to the check result signal 30 is counted by the counter 72 and the counter output 7
3 is output to the CONT 71, but when the number of errors exceeds a specified value, the counter output 73 is not output to the CONT 71, so that the CONT 71 can know that the data has been rewritten the specified number of times.

FIG. 6 is a block diagram showing the configuration of the data comparing section 8 in FIG.

The data comparing section 8 has a dummy read signal 15
Are active, a plurality of switch circuits 78 for outputting each bit of the stored data 29 as bit data 74
And a plurality of EX-s that perform an exclusive OR operation on each bit corresponding to each bit data 74 and data on the data bus 11.
It comprises an OR circuit 79 and an OR circuit 80 which performs a logical OR operation on the respective outputs of the EX-OR circuit 79 and outputs the result as a check result signal 30.

The data comparing section 8 compares the stored data 29, which is the data stored in the data / address holding section 4, with all the bits of the data read from the main memory 2, and if all the bits are the same, No error is output as a check result signal 30.

Next, the operation of this embodiment will be described with reference to FIGS.

FIG. 7 is a flowchart showing the operation of the memory monitoring system of FIG.

First, the CPU 1 writes data into the memory.
The specified address is output to the address bus 12 and the data to be written is output to the data bus 11. And
Activate the memory write signal 13. Since the memory write signal 13 has become active, the main memory 2 stores the data on the data bus 11 at the address specified by the address bus 12. Further, since the memory write signal 13 is activated, the data / address holding unit 4 stores the address of the address bus 12 and the data of the data bus 11, and the parity generation / check unit 5 generates the parity bit of the address of the address bus 12. Then, the data is output as parity data 28. The parity memory 6 stores the parity data 2 in the address specified by the address bus 12.
8 is stored. (Step 81) When the data writing is completed, the control unit 7
The Uwait signal 26 is activated to temporarily stop the operation of the CPU 1. Then, the dummy read instruction signal 21 is activated. The dummy read / dummy write signal generation unit 3 activates the dummy read signal 15 since the dummy read instruction signal 21 has been activated. Since the dummy read signal 15 has become active, the data / address holding unit 4 outputs the stored address to the address bus 12. Main memory 2 is memory read 1
The data / address holding unit 4 for performing a data reading operation is provided by a dummy read signal 15 input through the data / address holding unit 4.
Outputs the data stored at the address output by the data bus 11 to the data bus 11. (Step 82) Since the dummy read signal 15 via the memory read signal 14 becomes active, the parity memory 6 outputs the parity bit stored at the address indicated by the address bus 12 as the parity data 28. The parity generation / check unit 5 compares the data on the data bus 11 with the parity bits of the parity data 28, and performs a parity check to determine whether or not they correspond. Parity check generation /
The check unit 5 outputs an error to the parity result signal 27 if an error is detected by the parity check. If no error is detected, the control unit 7
The it signal 26 is released, and the CPU 1 returns to the normal operation. (Step 83) When an error is detected in the parity result signal 27, the control unit 7 activates the dummy write signal 22 and instructs execution of a rewrite operation. The dummy read / dummy write signal generator 3 activates the dummy write signal 16 when the dummy write instruction signal 22 becomes active. The data / address holding unit 4 outputs the dummy write signal 1
6 becomes active, the stored data is stored on the data bus 11 and the stored address is stored on the address bus 12.
Output to The main memory 2 has a memory write signal 13
Since the dummy write signal 16 input through the interface becomes active, the data on the data bus 11 is stored at the address specified by the address bus 12. (Step 84) When the dummy write operation in step 84 is completed, the control unit 7 activates the dummy read instruction signal 21 and instructs execution of the reread operation. The reread operation is performed in the same order as described in step 82. The data / address holding unit 4 outputs the dummy read signal 1
The stored data is output as the storage data 29 when the data 5 becomes active. (Step 85) The data comparison unit 8 compares all bits of the data read to the data bus 11 and the storage data 29, and outputs an error to the check result signal 30 if even one bit is different. If no error is detected, the control unit 7
The PUwait signal 26 is released, and the CPU 1 returns to the normal operation. (Step 86) When an error is detected in Step 86, Steps 84 and 8 are performed.
Operations 5 and 86 are repeated again. When the number of repetitions exceeds a certain value, the control unit 7 sets the CPU wait.
The signal 26 is released and the error signal 23 is sent to the CPU 1
To end the operation. (Step 88) Next, a description will be given with reference to a timing chart showing the operation of the memory monitoring method of the present embodiment in FIG.

FIG. 8A is a timing chart when no error is detected in the parity check.
(B) is a timing chart when an error is detected in the parity check and data rewriting and data comparison are performed.

First, FIG. 8A will be described.

After the CPU 1 writes the data to the main memory 2, the control unit 7 sends the CPU wait signal 26
To stop the operation of the CPU 1 and output the dummy read signal 15. The data / address holding unit 4 outputs the address held on the address bus 12, and the main memory 2 outputs the data stored at the specified address to the data bus 11. The output data is checked by the parity generation / check unit 5 with the parity data 28 and no error is detected.
, A signal indicating no error is output, and the CPU wait signal 26 is released.

Next, FIG. 8B will be described.

The operation from when the CPU wait signal 26 and the dummy read signal 15 are output until the address and data are output and the parity check is performed is the same as in FIG. 8A, but in this timing chart, the parity check is performed. Since an error is detected, the parity result signal 2
No signal indicating no error is output to 7. Therefore, the control unit 7 issues a data rewrite instruction and outputs a dummy write signal 16, and the data / address holding unit 4 outputs the stored data and address to the data bus 11 and the address bus 12, respectively. The memory 2 stores data at a specified address. Then, the dummy read signal 15 is output again, the data of the main memory 2 is read, and the data comparison unit 8 checks the storage data 29 stored in the data / address holding unit 4 and all bits, and the check result signal 30 Is output, the CPU wait signal 26 is released. When no error-free signal is not output, rewriting and re-reading operations are performed until an error-free signal is output or the number of repetitions exceeds a specified number.

[0057]

As described above, the present invention has the following effects. (1) When an error occurs in the data write operation, the data write can be executed again without depending on the software processing, so that the data can be rewritten at high speed. (2) Since all bits are checked after rewriting data, data reliability is improved as compared with parity check.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a memory monitoring method according to the present invention.

FIG. 2 is a configuration diagram of a dummy read / dummy write signal generation unit 3 in FIG.

FIG. 3 is a configuration diagram of a data / address holding unit 4 in FIG. 1;

FIG. 4 is a configuration diagram of a parity generation / check unit 5 in FIG. 1;

FIG. 5 is a configuration diagram of a control unit 7 in FIG.

FIG. 6 is a configuration diagram of a data comparison unit 8 in FIG. 1;

FIG. 7 is a flowchart showing an operation of the memory monitoring method of FIG. 1;

8 is a timing chart showing the operation of the memory monitoring method of FIG.

FIG. 9 is a block diagram of a conventional memory monitoring method.

FIG. 10 is a flowchart showing the operation of the memory monitoring method of FIG. 9;

[Explanation of symbols]

 1 CPU 2 Main memory 3 Dummy read / dummy write signal generator 4 Data / address generator 5 Parity generator / check unit 6 Parity memory 7 Control unit 8 Data comparison unit 11 Address bus 12 Data bus 13 Memory write signal 14 Memory read signal 15 Dummy read signal 16 Dummy write signal 21 Dummy read instruction signal 22 Dummy write instruction signal 23 Error signal 26 CPU wait signal 27 Parity result signal 28 Parity data 29 Storage data 30 Check result signal 31 Pulse generation circuit 32 System clock 33, 34 OR circuit 35 pulse signal 41 data memory 42 address memory 43 AND circuit 44 EX-OR circuit 45 address output instruction signal 46 memory instruction signal 51 parity generation / check Circuit 52 flip-flops 53, 54 switch circuit 55 parity output signal 56 parity input signal 71 CONT 72 counter 73 counter output 74 bit data 78 switch circuit 79 EX-OR circuit 80 OR circuit 81-88 step 91 CPU 93 dummy read signal generation Unit 94 address holding unit 111-114 step

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/16 310 G06F 12/16 320 G06F 11/10

Claims (6)

(57) [Claims] When writing data, an active memory write signal is output, data to be written is output to a data bus, and an address of written data is specified by an address bus. At the time of reading data, a memory read signal is activated to read data. A CPU that outputs an address to the address bus and stops operating while a CPUwait signal is active; and, when the memory write signal is input, stores data of the data bus at an address indicated by the address bus, and outputs the memory read signal. And a main memory for outputting data stored at the address indicated by the address bus to the data bus; and a dummy read instruction signal for causing the main memory to read data in a pseudo manner. Dummy And a dummy read / dummy for outputting a dummy write signal for causing the main memory to write data in a pseudo manner when the dummy write instruction signal is activated. A write signal generation unit, which stores the address of the address bus and the data of the data bus when the memory write signal is active and the dummy write signal is not active, and stores the data when the dummy write signal becomes active. And the address are output to the data bus and the address bus, respectively. When the dummy read signal is activated, the stored address is output to the address bus, and the stored data is output as storage data. A data / address holding unit, and the dummy read signal A data comparison unit that compares the data on the data bus with all the bits of the storage data when activated and outputs an error to a check result signal when even one bit is different; A parity memory that stores data stored at an address indicated by a bus and outputs data stored at an address indicated by the address bus as the parity data when the memory read signal is active; and A parity bit for data on the data bus is generated and output as the parity data. When the memory read signal becomes active, it is checked whether the parity data corresponds to the data on the data bus, and the result is used as a parity result. Paris output as a signal When the memory write signal becomes active, the CPU wait signal is made active after a predetermined time, a dummy read instruction signal is output, and if no error is detected by the parity result signal, the CPU wait signal is output. And the CPU is returned to normal operation. If an error is detected by the parity result signal, the dummy write instruction signal is activated, and then the dummy read instruction signal is activated, and an error is detected by the check result signal. If not, the CPU wait signal is released and the CPU is returned to the normal operation. If an error is detected by the check result signal, the dummy write instruction signal is activated again, and the dummy read instruction signal is activated. Depending on the check result signal This operation is repeated until the error is no longer detected, but if the number of times exceeds a certain number, the repetition operation of rewriting / reading the data is stopped, the CPUwait signal is released, and the CPU is returned to the normal operation. When the error signal is
A memory monitoring method configured with a control unit that outputs to a PU. 2. The system according to claim 2, wherein the dummy read / dummy write signal generating unit receives and divides a system clock and the system clock, and
A pulse generation circuit for generating a pulse signal having a cycle corresponding to one command signal; a first OR for performing a logical sum operation of the dummy read instruction signal and the pulse signal and outputting the dummy read signal
A second OR circuit that performs a logical sum operation of the dummy write instruction signal and the pulse signal and outputs the dummy write signal
2. The memory monitoring method according to claim 1, comprising a circuit. 3. An EX-OR circuit, wherein the data / address holding unit performs an exclusive OR operation of the memory write signal and the dummy write signal and outputs the result as a memory instruction signal, and the dummy write signal and the dummy read signal. AN that performs a logical AND operation with a signal and outputs it as an address output instruction signal
D circuit, when the memory instruction signal is input, the data of the data bus is stored, when the dummy write signal is input, the stored data is output to the data bus, and when the dummy read signal is input, the data is stored. A data memory for outputting the stored data as the storage data; an address memory for storing the address of the address bus when the memory instruction signal is input, and outputting the stored address to the address bus when the address output signal is input 2. The memory monitoring method according to claim 1, comprising: 4. A first switch circuit for outputting the parity data as a parity input signal when the memory read signal is active, wherein the parity generation / check unit outputs a parity output signal when the memory write signal is active. A second switch circuit that outputs the parity data, and a sum of the number of “1” bits included in the data of the data bus and the number of “1” bits included in the parity input signal is an odd number or an even number A parity generation / check circuit that outputs such a parity bit as the parity output signal, and a flip-flop that receives the parity output signal as input, receives the memory read signal as a clock input, and outputs the parity result signal. Item 2. The memory monitoring method according to Item 1. 5. The control unit according to claim 1, wherein the counter value in an initial state is zero, and when an error is output to the check result signal, the control unit adds one to the stored counter value, and the counter value exceeds a specified value. 2. The memory monitoring method according to claim 1, further comprising a counter unit that outputs the counter value as a counter output if the counter value is not present. 6. A plurality of switch circuits, wherein the data comparing section outputs each bit of the storage data as bit data when the dummy read signal is active, and a correspondence between each bit data and data of the data bus. EX-ORs that perform an exclusive OR operation on each bit
2. The memory monitoring method according to claim 1, comprising a circuit, and an OR circuit that performs a logical sum operation of outputs of the respective EX-OR circuits and outputs the result as the check result signal.