JP2536781B2 - Parity check device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a parity check device suitable for securing a check timing margin at the time of a parity check, and a check timing margin at the time of a parity check in response to an increase in speed of a computer system. In order to prevent the deterioration of reliability by ensuring the reliability of the data, a latch unit, a generate unit, and a check unit are provided, and the latch unit includes a latch clock, data, and data valid A control signal indicating that the data is output, and latches the data and the control signal at each latch clock cycle. The generate unit inputs the data output from the latch unit and outputs the logic in the data. It counts the number of "1" s and generates and outputs check data that indicates whether the number is even or odd. The check unit inputs the control signal output from the latch unit and the check data, determines whether the check data is correct or erroneous by the change in the control signal indicating the validity of the data, and outputs the result. Is configured to output.

[Industrial applications]

The present invention relates to a parity check device for detecting the presence / absence of an error in a binary code in a computer system or the like, and more particularly to a parity check device suitable for securing a check timing margin during parity check.

In recent years, with the demand for high reliability of computer systems, it has been required to add a parity bit to each data unit stored in a storage device to detect the presence or absence of data error. For this reason, various parity check methods have been provided, but it has become necessary to secure a margin of check timing at the time of parity check due to the speeding up of computer systems.

[Conventional technology]

FIG. 4 is a block diagram showing an example of a computer system including a parity check device. In the figure, 1 is a central processing unit (CPU), 2 is a main memory,
3 is a parity generation device, 4 is a parity check device, 5
Is an interrupt controller, 6 is a read / write (R / W) control signal, 7 is a data bus, 8 is a parity signal, 9 is an address bus, and 10 is an oscillator. In a computer system, an input / output device is generally configured,
It is omitted for simplicity of explanation.

In the above configuration, when data is written to the main storage device 2 by the CPU 1, the data is checked in the parity generation device 3 and, for example, when the even parity check is performed, the pits of the logical “1” are stored. A value of 1 pit is generated so that the number is even, and is added to the write data as a parity bit, and writing to the main storage device 2 is performed. On the other hand, when data is read from the main storage device 2, in the parity check device 4,
The read data and parity bit are checked to determine whether the number of pits that are logical "1" is an even number. Generate an NMI interrupt to CPU1.

FIG. 5 is a block diagram of a conventional parity check device 4. In the figure, 41 is a generation unit, 42 is a check unit, and the generation unit 41 inputs the data and parity bits read from the main storage device 2 and determines the number of bits that are logical "1". It counts and generates and outputs 1-bit check data indicating whether the counted number is an even number or an odd number.

The check unit 42 inputs the read control signal 6 from the CPU 1 and the check data, determines whether the check data is raw or erroneous, and outputs the result to the interrupt control device 5.

FIG. 6 is a time chart of the conventional parity check device 4. As shown in the figure, when the read control signal 6 becomes active (Low), the data and the parity bit from the main storage device 2 are output, and the generation unit 41 generates the check data by the data. It Then, at the time when the change of the control signal 6 to the inactive state is detected, the check unit 42 determines whether the check data is correct or incorrect and outputs the result. Therefore, the check data may not be generated in time, the valid data may not be determined at the time when the control signal changes, and the check result may be invalid.

[Problems to be Solved by the Invention]

However, in the above-described conventional technique, there are cases where the clock rate or the like is increased in a computer system to increase the speed, and in a different computer system or the like, the read cycle becomes short and the timing at which the control signal changes to inactive becomes early. Has occurred. In such a case, the check unit determines whether the check data is correct or erroneous and the margin for data generation in the generate unit cannot be secured, so that the parity check cannot be performed accurately and malfunction occurs. was there.

The present invention has been made in view of such a problem, and prevents a decrease in reliability by ensuring a check timing margin at the time of a parity check in response to a speedup of a computer system and the like. It is intended to provide a parity check device.

[Means for solving the problem]

FIG. 1 is a block diagram of the principle of the present invention. In the figure, the same parts as those in the prior art are designated by the same reference numerals.

As shown in FIG. 1, means for achieving the above-mentioned object in the present invention includes a latch section 43 and a generate section 41.
And a check unit 42, and the latch unit 43 inputs the latch clock, the data, and the control signal indicating the validity of the data, and latches the data and the control signal for each period of the latch clock. And the generate section 41
Receives the data output from the latch unit 43, counts the number of logical "1" s in the data, and generates check data indicating whether the number is even or odd. The check unit 42 outputs the data to the latch unit 43.
Inputting a control signal and the check data output from the control signal, determining whether the check data is correct or erroneous based on a change in the control signal indicating the validity of the data, and outputting the result. This is a characteristic parity check device.

(Operation) In the present invention, the latch unit 43 once latches the logical state of the data and the control signal indicating the validity of the data for each period of the latch clock, and inputs the latched data to the generate unit 41. , The control signal is input to the check unit 42. In the check unit 4, if the generating unit 41 can generate check data while the latched control signal is active, that is, while the latched control signal is active, the latched control signal becomes inactive. When it becomes a trigger, whether the check data is correct or incorrect is determined and the result is output. As a result, the control signal input to the latch unit 43 becomes inactive immediately after the data and the control signal are latched in the latch unit 43, and the generation of the check data to be judged by the generate unit 41 is started. Even if, check section 42
Since the control signal input to is not inactive until the next latch, it is possible to obtain a sufficient time required for the generation in the generate unit 41 to be determined.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram of a parity check device which is an embodiment of the present invention. The parity check device shown in the figure is configured in the computer system shown in FIG. 4, and the same components as those of the conventional configuration shown in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted. To do. In the figure, the generating unit 41 and the checking unit 42 operate in the same manner as the conventional one. 43a is a D-FF for data, 43b is a D-FF for parity, and 43c is a D-FF for control signal, to which a latch clock a generated by the oscillator 10 is input.

In the data D-FF 43a, the same number of D flip-flops as the data lines of the data bus 7 are formed, and the respective data lines are connected as input data. Therefore, the data is latched by the latch clock a and the latched data The signal b is sent to the generate unit 41. Parity D-FF
43b is one D flip-flop, to which the parity signal 8 is connected as input data, which is latched by the latch clock a and sends the latched parity signal c to the generate unit 41.

The control signal D-FF43c has one D flip-flop and is connected with the control signal 6 from the CPU 1 as input data. The control signal D is latched by the latch clock a and the latched control signal d is checked. Send to 42.

The generate unit 41 receives the latched data signal b and the latched parity signal c to generate check data e and sends it to the check unit 42. In the check unit 42, the change of the input latched control signal d from active to inactive is used as a trigger to determine whether the input check data e is correct or incorrect, and the determination result signal f is output to the interrupt control device. Send to 5.

FIG. 3 is a time chart in the above configuration.
As shown in the figure, when the read control signal 6 from the CPU 1 is active (Low) (), the data bus 7
And the read data is output from the main memory 2 to the parity signal line 8 (), and the data and the control signal are D- for data at the rising edge (A) of the latch clock a.
FF43a, D-FF43b for parity, D-FF43 for control signal
data signal b which is latched by each of c and
The parity signal c and the control signal d are output to the latch (B) at the next rising (,). The data for checking b and the parity signal c thus latched generate the check data in the generating section 41 (). When the control signal 6 input to the control signal D-FF 43c becomes inactive by the next rising (B) of the latch clock a, the control signal d input to the check unit 42 by the latch by the next rising. Becomes inactive (B), and at this time, the check unit 42
Then, the correctness / incorrectness of the input check data is judged and the result is output ().

As described above, in the present embodiment, the generation time of the check data in the generation unit 41 can be secured within one cycle of the latch clock regardless of the timing when the control signal from the CPU 1 becomes inactive. Further, by changing the period of the latch clock, it is possible to adjust the time corresponding to the required time.

〔The invention's effect〕

As described above, according to the present invention, even if the computer system is speeded up, the parity check can be performed without error, and by adjusting the latching interval, the computer system having different read cycles can be used. Since it is also applicable, it greatly contributes to improving the reliability of various computer systems.

[Brief description of drawings]

 FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a time chart in the embodiment, FIG. 4 is a block diagram of a computer system, and FIG. FIG. 6 is a block diagram of the parity check device, and FIG. 6 is a time chart in FIG. 1 ... CPU 2 ... Main control device 3 ... Parity generation device 4 ... Parity check device 5 ... Interrupt control device 6 ... Control signal 7 ... Data bus 8 ... Parity signal 9 ... Address bus 10 ... … Oscillator 41 …… Generate section 42 …… Check section 43 …… Latch section 43a …… Data D-FF 43b …… Parity D-FF 43c …… Control signal D-FF a …… Latch clock

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 62-259155 (JP, A) JP 60-95637 (JP, A) “Interface” 1981-3 (Vol. 46) CQ Publishing Co., Ltd. ) P. 95-108 (Z8000 memory design) 1981

Claims (1)

(57) [Claims] 1. A latch section (43) and a generate section (41)
And a check unit (42), and the latch unit (43) inputs the latch clock, the data, and a control signal indicating the validity of the data, and outputs the data and the control signal at each latch clock cycle. The generation section (41) inputs the data output from the latch section (43), counts the number of logic "1" in the data, and determines whether the number is an even number. It is for generating and outputting check data indicating whether there is an odd number or not, and the check section (42) inputs the control signal and the check data output from the latch section (43),
A parity check device, which is configured to determine whether the check data is correct or incorrect based on a change in a control signal indicating the validity of the data, and output the result.