JPH06348516A - Information processor - Google Patents

Abstract

PURPOSE:To enable a user to optionally select whether or not there is a check function and the kind of the check function as to the information processor which makes a parity check, an ECC check, etc. CONSTITUTION:When the user selects whether the check function is performed or not, specific values are set in registers 31 and 32 respectively under the control of a CPU. With the output of the register 31, a main memory controller 30 outputs an RAS/CAS signal for accessing a main memory in the selected state. IN the register 32, the value for placing a gate circuit 35 in a 'closed' state only when no check function is selected is set. Consequently, when the check function is selected, an NMI signal (non-maskable signal) is outputted normally through the gate circuit 35 on condition that a comparator 34 generates an unmatched comparison result, but when no check function is selected, the MNI signal is masked without fail.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device,
Especially, in order to improve the reliability of the main memory, parity check and ECC (error collecting code) are performed.
D: relates to an information processing device capable of performing an error correction code) check and the like.

[0002]

2. Description of the Related Art Information processing devices such as personal computers (hereinafter referred to as personal computers) and workstations include central processing units (CPU), storage devices such as main memory, input devices such as keyboards, printers and the like. It consists of an output device such as a display and an input / output device such as a floppy disk drive (FDD) or a hard disk drive (HDD), and usually has a check function to improve the reliability of the main memory. There is. As one of the checking functions, there has been a parity checking function for checking by adding a 1-bit code to the main memory, and the personal computer mainly uses this function.

The timing of reading data from the CPU of the information processing apparatus to the main memory depending on the presence or absence of this check function will be described. FIG. 10 is a timing chart of reading data from the CPU of the information processing apparatus to the main memory when the check function is not provided. In the figure, (A) is a clock CLK, and (B) is a row address strobe signal R.
AS, (C) is a column address strobe signal CAS,
(D) shows read data from the main memory.

Read data is performed as follows. First, at the rising edge of the second cycle of CLK shown in FIG. 9A, the RAS signal is dropped and the row address is given to the memory. Then, the CAS signal is made to fall at the same second falling edge of CLK as shown in FIG. 7C, and the column address is given to the memory. Then, from around the rising edge of the third cycle of CLK, as shown in FIG.
Data is read from the memory. This read data is taken into the CPU at the rising edge of the fourth cycle of CLK.

On the other hand, when the parity check function is provided, the timing of reading data from the CPU to the main memory is as shown in FIG. That is, FIG.
At the rising edge of the second cycle of the clock CLK shown in (A), the RAS signal is made to fall as shown in (B) of the figure, the row address is given to the memory, and then as shown in (C) of the figure.
The S signal is dropped at the falling edge of the second cycle of CLK,
Give the column address to memory. Then, 3 of CLK
Data and parity bits are output from the memory near the rising edge of the cycle as shown in FIGS.

The information processing apparatus generates a parity code from the output data among the output data and the parity bit, as shown in FIG. 11 (F), and compares it with the above output parity code. . If they match, the read data is read by the CPU at the rising edge of the fifth cycle of CLK.
Take in. If they do not match, an NMI (non-maskable interrupt) signal is generated and given to the CPU, as shown by the broken line in FIG. 11 (G), and the read data causes an error. Let me know.

As described above, in the case where the parity check function is provided (cycle number: 4 clocks), it takes an extra clock for reading as compared with the case where the parity check function is not provided (cycle number: 3 clocks). The same applies to writing to the memory.

By the way, the parity check function can detect data errors but cannot correct them. Therefore, there is an ECC check function for adding an error correction code of several bits to the data of the main memory to detect an error and which bit is an error. High-performance (high-priced) personal computers and workstations mainly use this ECC check function.

FIG. 12 is a timing chart of reading data from the CPU to the main memory when the ECC check function is provided. At the rising edge of the second cycle of CLK shown in FIG. 9A, the RAS signal is lowered and the row address is given to the memory, as shown in FIG. , CAS signal at the falling edge of the second cycle of CLK, and the column address is given to the memory. Then, in the vicinity of the rising edge of the third cycle of CLK, the memory outputs the data and the ECC data as shown in FIGS.

The information processing apparatus generates an ECC code from the output data among the output data and the ECC data as shown in FIG. 12 (F), and outputs the output ECC shown in FIG. 12 (E). Compare with the data. If they match,
The read data is loaded into the CPU at the rising edge of the sixth cycle of CLK. If they do not match, an NMI signal is generated, and at the timing shown by the broken line in FIG.
The data is output to the CPU to inform that the read data causes an error, or the data is corrected and the corrected data is given to the CPU.

As described above, when the ECC check function is provided (cycle number: 5 clocks), two clocks are extra for reading as compared with the case where the check function shown in FIG. 10 is not provided (cycle number: 3 clocks). Take The same applies to writing to the memory. If there is an error in the read data, it is necessary to correct the data, and it takes 1 or 2 clocks until the access to the memory is completed.

[0012]

Therefore, the parity check function and the ECC check function take a longer time than the case without the check function. But,
When a specific check function is configured by hardware, in the conventional information processing device, the user may stop checking,
Change to another check function (parity check function EC
When changing to C check function or vice versa)
Can not do it. Therefore, if the application software is, for example, game software,
Even when system reliability is not very demanding,
Even if the processing speed cannot be increased due to the check function, or conversely, system reliability is required, such as with communication software, an information processing device with a parity check function can achieve high performance. There is a problem that the ECC check function cannot be used.

It is an object of the present invention to provide an information processing apparatus which allows a user of the information processing apparatus to arbitrarily change the check function.

[0014]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention adds a check bit generated by a check bit generation unit to data from a central processing unit and stores it together with the data. For data and check bits written in the memory and check bits, an error check or error detection is performed based on the check bits, and an error notification is output to the central processing unit when an error bit is detected. Input means for designating the presence / absence of the check function, access means for accessing the memory at a predetermined timing according to the presence / absence of the check function designated by the input means, and when no check function is designated by the input means The output of the error notification is masked in the memory and a check function is provided by the input means. When There is designated, unmask is obtained by a structure having a mask control means for the output state of the error notification.

The check function can be provided in a plurality of types. In this case, the access means accesses the memory at the timing corresponding to the absence of the check function and the absence of the check function designated by the input means among the plurality of types of check functions or the type of the check function. be able to. The check bit generation unit may be configured to switch and generate the check bit of the type of the check function designated by the input means.

According to the present invention, when the check function is selected by the input means, the check bit is checked for each data read from all the addresses of the memory after the error notification is masked by the mask control means. A rewrite unit that generates a check bit by the generation unit and rewrites the read data together with the corresponding generated check bit at the same address of the read data, and a mask for the error notification after the writing by the rewrite unit is completed. It can further have a mask releasing means for releasing.

[0017]

According to the present invention, when the user selects at least one of the check function and the non-check function by the input means, the access means accesses the memory optimum for the selected function. When "No" is selected, the processing such as data reading from the central processing unit to the memory can be sped up as compared with when the check function is provided. When the check function is selected, more reliable processing can be performed than when the check function is not selected. Therefore, in the present invention, the user can arbitrarily switch the presence or absence of the check function according to the type of application software. Also, when there are multiple types of check functions,
The type of check function can also be switched.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS.
Will be explained together. 1 is a configuration diagram of a first embodiment of an information processing apparatus of the present invention, FIG. 2 is a configuration diagram of an embodiment of a main part of FIG. 1,
FIG. 3 is an external view of the device according to the first embodiment of the present invention.

In FIG. 1, a central processing unit (CPU)
1, main memory 2, dynamic random access memory (DRAM) controller 3, keyboard 4
The display device 5 and the display device 5 are connected to each other via a bidirectional bus 6. Although not shown, FDD and HD
Input / output devices such as D are also connected to the bus 6. Further, an input device other than the keyboard 4 such as a mouse or an output device other than the display device 5 such as a printer may be connected to the bus 6.

The CPU 1 is connected to another device 2 via the bus 6.
.. and 5 to exchange addresses and data and control these operations. In addition, the CPU 1 sends the signal via the signal line 7.
The control signal is output to the DRAM controller 3. The control signals are an ADS (address strobe) signal, an MIO (memory, I / O discrimination signal) signal, and a WR (write / read discrimination signal) signal.

The main memory 2 is composed of a DRAM and is a data storage section 2 which is a storage area for storing data.
a and a parity storage unit 2b which is a storage area for storing a parity bit. The DRAM controller 3 reads the main memory 2 by the configuration described later,
Write and refresh control. Also, DRA
The M controller 3 sends N to the CPU 1 via the signal line 8.
The MI signal is output, the RAS signal and the CAS signal are supplied to the main memory 2 via the signal line 9, and the parity bit is exchanged with the parity storage unit 2b via the signal line 10.

The DRAM controller 3 is constructed as shown in FIG. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In FIG.
The DRAM controller 3 includes a main memory controller 30, a first register 31, a second register 32, a parity bit generation unit 33, a comparator 34, a gate circuit 35,
It is composed of an input driver 36 and an output driver 37.

The main memory controller 30 is a RAS.
The / CAS signal is generated and output to the main memory 2 via the signal line 9 to control the main memory 2. The first register 31 is a register for controlling whether or not the parity check function is added, and by supplying the information to the main memory controller 30, the data is read from the main memory 2 at the timing shown in FIG. It is controlled whether the data is read or the data is read and checked at the timing shown in FIG.

The second register 32 is a register for controlling whether or not to mask the NMI signal generated by the comparator 34, and outputs the mask signal to the gate circuit 35. The parity bit generation unit 33 receives the CP input via the bus 6.
It is a circuit that generates a parity bit based on data from the data storage unit 2a of U1 or the main memory 2. The comparator 34 includes a parity bit generated by the parity bit generation unit 33 and the parity storage unit 2b of the main memory 2.
Is compared with the parity bit read from the input driver 36 and input through the input driver 36.
Generate a signal. The gate circuit 35 is a logic circuit that determines whether or not the NMI signal generated by the comparator 34 is masked by the signal from the second register 32.

The above CPU 1, main memory 2 and DRA
The M controller 3, the bus 6, and the signal lines 7 to 10 are stored in the information processing apparatus main body 11 shown in FIG. Also,
The keyboard 4 and the display device 5 are, as shown in FIG.
It is installed at an arbitrary position outside the information processing apparatus main body 11. The display device 5 uses a cathode ray tube (CR
It is a CRT display that displays characters and figures at T).

Next, the operation of this embodiment will be described.
First, a case where the user of the information processing apparatus wants to set the parity check function to "none" will be described. in this case,
The user operates the keyboard 4 to display the check function switching menu as shown in FIG. 3 on the screen 5a, and the check function of the menu is (1) "none", (2) )
(1) is selected from among the “parities”. If the wrong number is entered, the information processing device prompts the user to re-enter the number.

When (1) is correctly input, the CPU 1
Recognizes it, and as shown in FIG.
The message of "There is no check function" is displayed on screen 5
a and the DRAM controller 3 of FIG.
A predetermined first value is set in the first register 31 therein. When the first value set in the first register 31 is input to the main memory controller 30, the main memory controller 30 causes the main memory 2 to access the main memory 2 at the timing shown in FIG. And a CAS signal are generated and output to the main memory 2.

The CPU 1 also sets a predetermined second value in the second register 32 in the DRAM controller 3. The second value set in the second register 32 is
It is supplied from the second register 32 to the gate circuit 35,
The gate is closed, and the comparison result of the comparator 34 is masked so that the NMI signal on the signal line 8 does not become active even if the comparison result of the comparator 34 does not match.
This prevents the NMI signal on the signal line 8 from becoming active and the CPU 1 from being illegally interrupted.

Therefore, when the user selects (1) without the check function, the main memory 2 is accessed at the timing of FIG. 10, so that the memory access 1 is compared with the case with the parity check function. Since the access can be performed by one clock less each time, the processing speed of the information processing apparatus can be increased as compared with the case where the parity check function is provided.

On the other hand, when the user selects (2) with the parity check function, the CPU 1 recognizes it and sets a predetermined third value in the first register 31 in the DRAM controller 3. Set. When the third value set in the first register 31 is input to the main memory controller 30, the main memory controller 30 causes the main memory 2 to access the main memory 2 at the timing shown in FIG. And a CAS signal are generated and output to the main memory 2.

The CPU 1 also sets a predetermined fourth value in the second register 32 in the DRAM controller 3. The fourth value set in the second register 32 is
It is supplied from the second register 32 to the gate circuit 35,
The gate is opened, and the comparison result of the comparator 34 passes through the gate circuit 35 as it is and is output to the signal line 8.

On the other hand, the comparator 34, when reading the main memory 2, reads the read data from the data storage unit 2a of the main memory 2 in the parity bit generation unit 33 and the parity bit read from the parity storage unit 2b. And are compared, and only when they do not match, a comparison result of a predetermined logic level is output. The comparison result of the predetermined logic level passes through the gate circuit 35 as it is and activates the NMI signal on the signal line 8.

Further, when the comparator 34 outputs the judgment result that the above two input parity bits match, the NMI signal is not activated even when the gate circuit 35 is in the gate "open" state. In this way, the NMI signal is output to the CPU 1 only when the comparator 34 obtains a mismatched comparison result, and the CPU 1 is normally interrupted.
The reliability of the entire information processing apparatus can be maintained.

As described above, according to this embodiment, the user of the information processing apparatus can switch the presence / absence of the parity check function depending on the intended use. For example, when the system reliability is not so required, such as game software, the check function can be omitted to speed up the process. On the contrary, if you need system reliability such as communication software, use with check function.
The reliability of the entire information processing device can be maintained. Therefore, in the present embodiment, the processing speed can be increased and the usability can be improved according to the type of application software.

Next, the second embodiment of the present invention will be described with reference to FIG.
9 to FIG. In the first embodiment described above, the check function is only the parity check function,
The present embodiment is an example in which either the parity check function or the ECC check function can be selected as the check function. 4 is a block diagram of a second embodiment of the information processing apparatus of the present invention, FIG. 5 is a block diagram of an embodiment of the main part of FIG. 4, and FIG.
8 to 8 are flowcharts for explaining the operation of the second embodiment, and FIG. 9 is an external view of the apparatus of the second embodiment. 4 and 5
The same components as those in FIGS. 1 and 2 are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 4, the main memory 12 has a DR
A data storage unit 12a, which is a storage area configured to store data and stores data, and a parity bit or ECC.
The check bit storage unit 12b is a storage area for storing codes (collectively referred to as check bits). The DRAM controller 13 controls the reading, writing and refreshing of the main memory 12 by the configuration described later. Further, the DRAM controller 13 exchanges data and the like with the CPU 1 via the bus 14, exchanges data with the data storage unit 12a of the main memory 12 via the bus 15, and Check bits are exchanged with the check bit storage unit 12b via the signal line 16. Furthermore, CPU
1 is connected to a keyboard 4, a display device 5, and the like via a bus 17.

The DRAM controller 13 is constructed as shown in FIG. In the figure, parts that are the same as the parts shown in FIG. 4 are given the same reference numerals, and descriptions thereof will be omitted. 5, the DRAM controller 13 includes a main memory controller 130, a first register 131, a second register 132, switch circuits 133 and 145, a check bit generator 134, a comparator 135, and gate circuits 136 and 13.
7, data correction unit 138, input drivers 139, 14
1, 143 and output drivers 140, 142, 144
Consists of.

The main memory controller 130 is an RA
The main memory 12 is controlled by generating an S / CAS signal and outputting it to the main memory 12 via the signal line 9. The first register 131 is a register for controlling whether or not the check function is added, and by supplying the information to the main memory controller 130, data is read from the main memory 12 at the timing shown in FIG. It is controlled whether the data is read or at which of the timings shown in FIGS. 11 and 12, the data is read and checked.

The second register 132 is a register for controlling whether or not to mask the NMI signal generated by the comparator 135, and outputs a mask signal to the gate circuit 136.
The check bit generation unit 134 includes the bus 14 and the input driver 139 or the bus 15 and the input driver 1.
CPU 1 or main memory 1 input via 43
2 is a circuit for generating check bits based on the data from the data storage unit 12a of the main memory controller 13
Based on the control signal from 0, parity bit or E
Generate CC code.

The comparator 135 includes a check bit generator 1
The check bit generated in 34 is compared with the check bit read from the check bit storage unit 12b, and if they do not match, an NMI signal is generated. The gate circuit 136 is a logic circuit that determines whether or not the NMI signal generated by the comparator 135 is masked by the signal from the second register 132. Switch circuit 133
Switches between write data from the CPU 1 to the main memory 12 and read data from the data storage unit 12a of the main memory 12, and the check bit generation unit 13
Give to 4.

The data correction unit 138 inputs the main memory 12 via the bus 15 and the input driver 143.
It is checked whether or not there is an error in the read data from the data storage unit 12a, and if there is an error, the erroneous data and the ECC code input via the bus 16 and the input driver 141 are detected. The correction is performed using a predetermined generator polynomial. The data correction unit 138 performs a correction operation when the comparison result indicating the mismatch is input from the comparator 135. In addition, the gate circuit 137 is
It is a gate for generating a control signal for controlling switching of the switch circuit 145. The switch circuit 145 is
The read data from the data storage unit 12a of the main memory 12 is directly transmitted to the bus 1 via the output driver 140.
4 or output the read data to the data correction unit 138.
The result corrected in step 1 is output to the bus 1 via the output driver 140.
The output to 4 is switched. Second register 132
Sets the NMI mask release and the read data has an error, the corrected data is output to the bus 14 via the output driver 140.

The above CPU 1, main memory 2, and DRA
The M controller 13, the buses 14, 15, 17 and the signal lines 7-9, 16 are stored in the information processing apparatus main body 21 of FIG.

Next, the operation of this embodiment will be described with reference to the flowcharts of FIGS. 6 to 8. When the user of the information processing device performs a predetermined operation using the keyboard 4, the CPU 1 first displays a check function switching menu on the screen of the display device 5 according to the flowcharts of FIGS. (Step 201 in FIG. 6). The check function switching menu is a character string from the first line to the third line from the top of the screen 5a of the display device 5 of FIG. It is a display for selecting any one of (1) none, (2) parity check, and (3) ECC check.

Therefore, the following input data is "1" to "
Since it is any number of "3", the CPU 1 determines that there is a subsequent key input from the keyboard 4 (step 202 in FIG. 6), the input data is "1" to "".
3 "(step 203 to step 203).
205), when data other than any of these numbers is input, it is determined that an incorrect number (for example, 4) has been input, and a message prompting re-input of the number is displayed (at step 201).

Now, assuming that the user inputs "1", the CPU 1 recognizes that, and the first register 131 in the DRAM controller 13 of FIG.
The predetermined fifth value of the bit is set and the process without the check function is performed (step 206 in FIG. 6). When the fifth value set in the first register 31 is inputted to the main memory controller 130, the main memory controller 130 causes the main memory controller 130 to access the main memory 12 at the timing shown in FIG. And CAS
A signal is generated and output to the main memory 12.

The CPU 1 also sets a predetermined sixth value in the second register 132 in the DRAM controller 13 (step 207 in FIG. 7). This second register 1
The sixth value set to 32 is supplied from the second register 132 to the gate circuit 136 to gate it “closed”.
Even if the comparison result in the comparator 135 does not match, the NMI signal on the signal line 8 is not activated,
NMI mask setting is performed to mask the comparison result of the comparator 135. This prevents the NMI signal on the signal line 8 from becoming active and the CPU 1 from being illegally interrupted. Subsequently, the CPU 1 sets the seventh value in the first register 131 and controls the main memory controller 130 to prohibit the operation of the check bit generation unit 134 (step 20 in FIG. 7).
8), the process ends.

As described above, also in this embodiment, when "no check function" is selected, the main memory 12 can be accessed at the timing shown in FIG. 10, so that the ECC check function is provided (access timing in FIG. 12). In comparison, since each memory access can be performed by 2 clocks less, the processing speed of the information processing device can be improved.

Next, the operation of this embodiment when the check function is selected will be described. The user sees the check function switching menu on the screen 5a in FIG.
6 is pressed, the process proceeds from step 204 of FIG. 6 to step 209, the process of adding the parity check function is performed, and when the number “3” is keyed in, the process of FIG.
From step 205 to step 210, the process of adding the ECC check function is performed. In the processing of adding the parity check function described above, the CPU 1 executes the first register 13
By setting the predetermined 2-bit eighth value to 1,
This is a process for causing the main memory controller 130 to generate the RAS signal and the CAS signal for accessing the main memory 12 at the timing shown in FIG. In the processing of adding the ECC check function described above, the CPU 1 sets the predetermined 2-bit ninth value in the first register 131 to cause the main memory 12 to operate in the main memory 12 at the timing shown in FIG. RA to access
This is a process of generating the S signal and the CAS signal and outputting them to the main memory 12.

If the user changes the state without the check function to the parity check function or the ECC check function, the data in the main memory 12 is stored in the CPU.
When 1 is read, the NMI signal may be illegally generated. This is because the correct parity bit and ECC code are not stored in the check bit section 12b in the state without the check function. Therefore, when the check function is provided, the parity check function stores the parity bit generated from the read data and the check bit storage unit 12 in the parity check function.
Comparing with the parity bit from b, there is a mismatch (there is a possibility that more than half will be mismatch in the case of a parity check), an NMI signal is generated, and an illegal interrupt is input to the CPU 1.

Similarly, in the ECC check function, when the ECC code generated from the read data of the data storage unit 12a and the ECC code from the check bit storage unit 12b are compared, they do not match (most of them do not match in the case of ECC check). Therefore, an NMI signal is generated and an illegal interrupt is input to the CPU 1.

Therefore, in this embodiment, in consideration of the case where the state without the check function is switched to the state with the check function, the parity check function or the ECC check function is selected (in FIG. When "2" or "3" is entered by key input, step 20 in FIG.
9 Parity check function addition processing or step 2
After executing the process of adding the ECC check function of 10, the processes of step 211 onward in FIG. 8 are performed.

That is, first, in step 211, the same NMI mask setting as in step 207 is set. After that, a predetermined value is set in the register 131, the check bit generator 134 is made operable by the main memory controller 130, and the mask of the check function (parity check function or ECC check function) is released (step 212). At this time, the set value of the register 131 indicates whether the check bit generation unit 134 generates a parity bit or an ECC code.

Next, in order to add check bits to all the data in the main memory 12, the CPU 1 reads the data from the data storage section 12a (step 2).
13), a check bit generation unit 134 for the check bits (parity bit or ECC code) of the designated type
(Step 214), the generation check bit is added to the read data which is the generation element,
The data is written again in the same address as the read address of the data in the main memory 12 (step 215). This operation is performed for all addresses in the main memory 12 (step 216,
217, 212-215). Check bit generation and main memory 1 for all addresses in main memory 12
When the writing of the data and the check bit to 2 is completed, the second register 132 is set to a predetermined value,
The gate circuit 136 is set to the gate “open” state, and the NMI mask is released (step 218).

By the above processing, correct check bits can be added to all the data in the main memory 12. In addition, there are cases where it takes several seconds until the processing for adding the check function is completed (for example, when a large-capacity main memory of 64 MB or more is installed in the information processing apparatus).
As described above, a message such as "ECC code is added to the main memory, please wait for a while." Is displayed on the screen 5a of the display device 5.

After releasing the NMI mask in step 218, the information processing apparatus executes the operation of the selected check function. For example, when the user key-in the number "3" as shown in FIG. 9 and selects the item (3) with the ECC check function, the CPU 1 recognizes it and executes the steps 210 to 217. Via the DRAM controller
The main memory 12 is continuously accessed at the timing shown in FIG. 12 by the controller 130, and the operation is controlled so that the check bit generator 134 generates an ECC code. Therefore, the comparator 135 uses the generated ECC code from the check bit generation unit 134,
Main memory 12 input via input driver 141
Compare the read ECC codes from.

The result of this comparison is the result of step 218 described above.
Since the NMI mask is released at, the gate circuit 13
The signal is directly output to the signal line 8 without being masked by 6. Therefore, when the generated ECC code from the check bit generation unit 134 does not match the read ECC code from the main memory 12 input via the input driver 141, the comparison result output from the comparator 135 does not match. Is output as an active NMI signal through the gate circuit 136, and the interrupt is normally input to the CPU 1.

The comparison result of the comparator 135 is also supplied to the gate circuit 137 and the data correction unit 138. The gate circuit 137 is connected to the register 13
The switch circuit 145 is connected to the terminal b side only when the predetermined value for canceling the NMI mask is input from 2 and the comparison result indicating the mismatch is input from the comparator 135.
In other cases, it is controlled to connect to the terminal a side. Further, the data correction unit 138 is read from the data storage unit 12 a of the main memory 12 only when the comparison result indicating the mismatch is input from the comparator 135, and the bus 1
5 and the input driver 143, the ECC code from the check bit storage unit 12b input via the bus 16 and the input driver 141, and a predetermined generator polynomial are used to correct the error bit.

Therefore, when the NMI signal becomes active, the read data from the data storage unit 12a of the main memory 12 has the error bits corrected by the data correction unit 138 to become correct data. This correct data is the switch circuit 145, the output driver 140 and the bus 14.
The reliability of the entire information processing apparatus can be maintained because the data is input to the CPU 1 via each of the.

In FIG. 5, when writing data, the data from the CPU 1 is output to the data storage section 12a of the main memory 12 via the bus 14, the input driver 139, the output driver 144 and the bus 15, respectively. The data from the input driver 139 is input to the check bit generation unit 134 through the switch circuit 133, converted into the check bit (parity bit or ECC code) selected here, and then output driver 1
42 and the bus 16 respectively through the main memory 12
Is input to the check bit storage unit 12b.

When the user selects the parity check function (2), the data correction unit 138 outputs the read data input via the input driver 143 without performing the correction operation.

As described above, according to this embodiment, one of the parity check function and the ECC check function, which are functions for improving the reliability of the main memory, and the mode in which these check functions are not used. The user who uses the information processing device can be arbitrarily switched, and the processing speed can be increased and the usability can be improved.

The present invention is not limited to the above embodiments, and for example, the types of check bits stored in the check bit storage section 12b of the main memory 12 and the data read from the main memory 12 are performed. A means for detecting whether or not the type of check function selected by key input at the same time is the same is provided, and when the check function is the same, the reading by the selected check function is immediately performed without executing the processing shown in FIG. It may be executed. Further, it goes without saying that the processing of FIG. 8 may be applied to the first embodiment.

[0063]

As described above, according to the present invention, the user can arbitrarily switch the presence or absence of the check function according to the type of application software.
Depending on the user's intention to prioritize speeding up the processing or ensuring the reliability of the data, it is possible to speed up the processing and improve the usability, thus improving the performance of the entire information processing device. can do. In addition, since the parity check function and the ECC check function can be switched, it is possible to secure the reliability of necessary and sufficient data according to the intention of the user.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an embodiment of a main part of FIG.

FIG. 3 is an external view of the device according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

5 is a block diagram showing a configuration of an embodiment of a main part of FIG.

FIG. 6 is a flowchart (part 1) for explaining the operation of the second embodiment of the present invention.

FIG. 7 is a flowchart (part 2) for explaining the operation of the second embodiment of the present invention.

FIG. 8 is a flowchart (No. 3) for explaining the operation of the second embodiment of the present invention.

FIG. 9 is an external view of the device according to the second embodiment of the present invention.

FIG. 10 is a time chart showing a memory read timing without a check function.

FIG. 11 is a time chart showing a memory read timing when a parity check function is provided.

FIG. 12 is a time chart showing a memory read timing when the ECC check function is provided.

[Explanation of symbols]

1 ... Central processing unit (CPU), 2, 12 ... Main memory, 2a, 12a ... Data storage unit, 2b ... Parity storage unit, 3, 13 ... DRAM controller, 4 ... Keyboard, 5 ... Display device, 6, 14, 15, 16, 17 ... Bus, 7-10, 16 ... Signal line, 12b ... Check bit storage unit, 30, 130 ... Main memory controller, 3
1, 131 ... First register, 32, 132 ... Second register, 33 ... Parity bit generator, 34, 135 ...
Comparator, 35, 136 ... Gate circuit for NMI mask, 1
33, 145 ... Switch circuit, 134 ... Check bit generation unit, 138 ... Data correction unit

Claims (1)

[Claims] 1. A check bit generated by a check bit generation unit is added to data from a central processing unit and written to a memory together with the data, and data and check bits read from the memory are Error check or error detection based on the check bit,
When an error bit is detected, in an information processing device that outputs an error notification to the central processing unit, at least an input means for designating the presence / absence of a check function, When the check function is not specified by the access means for accessing the memory at the timing and the input means, the output of the error notification is masked to the memory and the check function is specified by the input means. And a mask control means for canceling the mask to put the error notification in an output enabled state when the information processing apparatus is operated.