JPS59163651A - Parity checking device for program data - Google Patents

Abstract

PURPOSE:To obtain the accurate parity information from a program loader of high reliability by storing successively the parity bits produced every byte of the ROM data to an RAM for parity when the program data including the ROM data is loaded. CONSTITUTION:An ROM1 of a parity checking device stores the system monitor, data, a part of a program, etc., and an RAM2 stores the parity bit of the ROM data including an initial program loader. The data of the ROM1 is applied to a parity checking circuit 4 when a reading gate 3 is set in a reading mode, and this data is checked with the parity bit given from the RAM2. Then a parity error, if detected, is applied to an AND gate 7, and an AND is obtained with the output of an FF6. Then a parity error signal of each byte of data is delivered to a CPU. Thus the parity information is obtained from a program loader having high reliability of data. This ensures an accurate parity check.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a parity check device for program data stored in an 8-bit ROM including a non-volatile RAM such as FROM.

(b1 Background of the Invention Generally used ROM (including non-volatile RAM such as FROM) has an 8-bit configuration (for example, 16K
X8 bits), and a parity bit is not normally added as information on the 9th bit. However, even ROM has a certain failure rate expressed in MTBF, so if garbled data in RAM has a large impact on the system, it is necessary to provide a parity bit to ensure reliability. In order to meet such demands, for example, a parity addition program is prepared inside the ROM, and when the power is turned on, the program data stored in the ROM itself is read out, a parity bit is generated, and the program is used for parity storage. One possible method is to store it in an appropriate area of RAM.

However, in this method, the original data for generating the parity bit is program data stored in the ROM itself, so if the inside of the ROM has already been destroyed, the generated parity bit itself will not be correct. That is, there is a drawback that the reliability of the parity bit is lacking.

(C1 Purpose of the Invention The purpose of the present invention is to provide a parity check device that can more accurately perform a parity check on program data during program execution by obtaining parity information from a program loader with high data reliability. shall be.

(Structure and Effect of dJ Invention) To summarize, the present invention consists of a parity storage R for sequentially storing parity bits generated for each byte of ROM data when program data including ROM data is loaded.
AM is provided, and the parity focus of Rik:M data is obtained based on data from the program loader.

According to this invention, the reliability of the parity bit is significantly improved because the parity bit is not generated from the ROM itself (but is generated based on data from a highly reliable program loader), and the parity bit is generated based on data from a highly reliable program loader. It is possible to reliably generate a parity error when destroyed.

(e) Embodiment FIG. 1 is a block diagram of a parity check device which is an embodiment of the present invention. In the figure, 1 is a 16Kx8-bit ROM, and as shown in FIG.
ial Program, oader), system monitor, l0C3, etc. 2 is 16KX1
It is a bit RAM and stores parity bits of ROM data including IPL. The READ gate 3 outputs read data from the ROMI to the CPU data bus in the READ mode. The parity check circuit 4 is a ROMI
The parity of the 8-bit read data from the RAM 2 is checked using the parity bit from the RAM2. If there is a parity error, the error signal is sent to CP via AND gate 7.
Output to U. A parity check circuit operation start signal and a system reset signal are OR-input to the set terminal S of the flip-flop 6, and a parity check circuit operation stop signal is input to the reset terminal R. Further, the set output terminal Q is connected to an AND gate 7. From the above configuration, when the flip-flop 6 is in the sent state, that is, after the parity check circuit operation start signal or system reset signal is input until the parity check circuit operation stop signal is input, the RO is in the READ mode.
A parity check is performed on the data read from M1, and if there is a parity error, an error signal is sent to the CPU.

Next, the procedure for writing the parity bit into the RAM 2 will be explained with reference to FIG. Figure 3 (A) is IPL
It is a flowchart which shows the main part of an execution procedure.

First, the program is started from address $0000 ($: symbol representing a hexadecimal number) at step nl (hereinafter, step ni is simply referred to as ni). Address $
0000 is the first address of the IPL. Set the setting state of the program load execution/non-execution switch (not shown) to n2.
, and proceed to n3 only when loading, then judge the setting status of the parity generation rate setting switch (not shown), and proceed to n4 if parity generation is to be performed, and skip to n5 if not to generate parity. Proceed to. A case where there is no need to execute a program load after power is turned on is a case where all RAM is configured as non-volatile, and in such a case, it is not necessarily necessary to execute a program load. Further, the reason why the operation of the parity check circuit is stopped at n4 when parity generation is performed at n3 is because it is necessary to prevent a parity error from occurring when reading the PL itself. After completing the above processing, start the program loader at n5 below, and n
In step 6, the data input from the program loader is $
Store in order from OOOO to $FFFF. When the loading is completed, the operation of the parity check circuit 4 is restarted at 07, and execution of the general program is started. Note that at n4, a parity check circuit operation start signal is applied to the cent terminal of the flip-flop 6, and at n7, a parity check circuit operation stop signal is applied to the reset terminal of the flip-flop 6.

FIG. 3(B) is a flowchart showing the data loading procedure at n6.

First, the store address is set to $0000 using n60. Next, at n61, 1 byte data is read from the program loader, a parity bit of the data is generated (n62), and a write command is issued for the data with parity (n63). In n63, parity data is written to RAM2, but since ROM data at this time cannot be written (ROMI is FROM), it is actually ignored. When writing of the 1-byte parity bit is completed, the store address is incremented at n64 and the process returns to n61. Loading ends when the processing of n61 to n64 is completed for all addresses.

By the above procedure, when the program data is loaded after the power is turned on, the parity bit corresponding to the ROM data can be stored in RAM2.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a parity check device that is an embodiment of the present invention, FIG. 2 is a memory configuration diagram used in a system to which the parity check device is applied, and FIG. 3 (A)
, (B) is a flowchart showing the main part of the operation procedure of IPL. 1-ROM, 2-RAM (for parity storage). 4-Parity check circuit. Applicant Tateishi Electric Co., Ltd. Agent Patent Attorney Hisao Komori

Claims (1)

[Claims] (1) A parity storage RAM that sequentially stores parity bits generated for each byte of the ROM data when loading program data including ROM data, and a parity storage RAM that stores the program data in the RAM when executing a program stored in the ROM. A parity check device for program data, comprising: a parity check circuit that performs a parity check using a stored parity bit.