JPH01137474A - Data storage controller - Google Patents

Abstract

PURPOSE:To easily recognize a read error due to the interruption of the write operation of a high-order device by inverting the polarities of the number of data, which an ECC (error correction code) has the correction capability for, to write data. CONSTITUTION:When the number 4 of write data received from the high-order device and the counted result of a reception write data set signal 5 are compared with each other at the time of starting write to detect that the write operation is interrupted by the trouble of the high-order device, the write operation is immediately interrupted, but the write operation terminating sequence adds the ECC to data, which is sent till then, to write data on a medium in the same manner as normal termination. Polarities of only the number of data which the ECC has the correction capability for are inverted to write data, and thereby, it is tested whether a corrected pattern is all '1' or not. Thus, the read error due to interruption of the write operation of the higher-order device is recognized in distinction from normal read error.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data storage control device such as a magnetic disk control device used in an information processing device, and particularly relates to an improvement of a write control circuit.

[Conventional technology]

Conventional data storage devices, especially magnetic disk control devices that control magnetic disk devices widely used as external storage devices for information processing devices, write data received from a host device and receive write data set signals directly to the magnetic disk. Since the data is being sent to the device, if an error occurs in the host device during a write operation, the write operation will be interrupted, and the magnetic disk device will apply ECC (Error Correction) to the data sent up to that point.
Write data on the medium without adding Code).

[Problem that the invention seeks to solve]

In the conventional control device described above, when reading data written when an abnormality occurs in the host device, a read error occurs, but the problem appears to be caused by the magnetic disk device, and the problem occurs when the host device However, it is not possible to detect a read error due to interruption of a write operation, resulting in incorrect maintenance.

[Means for solving problems]

The data storage control device of the present invention stores received write data number information sent from a host device in a write data number set signal, outputs it as write data number information, and simultaneously counts and receives received write data set signals. The host device abnormality detection circuit detects that the write operation is interrupted before receiving the same number of received write data set signals as the write data count information, and the received write data set when the received write command signal that instructs to write data becomes active. The ECC data selection signal is set to 7 to immediately terminate the write operation when the above-mentioned host device abnormality detection circuit monitors whether the signal matches the write data number information and activates the ECC.
Start writing (error collection code)^,
Moreover, to indicate that a write abort operation has occurred, the ECC
The ECCj data inversion instruction circuit outputs an ECC data inversion instruction signal that instructs to invert only the number of data (for example, 1 byte) within the correction capability of the controller, and the ECCj data inversion instruction circuit outputs an ECC data inversion instruction signal that instructs to invert the polarity of only the number of data (for example, 1 byte) that is within the correction capability of the controller. The write information temporarily accumulated by the received write data set signal is used as write data, and while the ECC data selection signal is active and the ECC data inversion instruction signal is inactive, the ECC information temporarily accumulated by the ECC data set signal is written. data, the ECC data selection signal is active, and the ECC
When the data inversion instruction signal also becomes 7 active at the same time, E
and a write data editing circuit that outputs CC information with polarity inverted as write data.

The data storage control device of the present invention detects that the write operation has been interrupted due to a failure in the host device by comparing the number of write data received from the host device at the start of writing with the result of counting the received write data set signals. , the write operation is immediately interrupted, but the write operation end sequence is similar to the normal end, and ECCCError Correction C is applied to the data sent so far.
ode ) to write the data on the medium. However, the number of data within the correction capacity of the ECC (for example, 1
By inverting the polarity of only the byte (byte) and writing data, when a read error occurs, a correction operation is performed, and the read error is correctable and the correction position is ECC.
It is tried whether the correction pattern also becomes all "1" in the part. Thereby, it is possible to clearly distinguish a read error caused by interruption of the write operation of the host device from a normal read error. .

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a magnetic disk control device which is a data storage control device.

Referring to FIG. 1, the host device abnormality detection circuit 1 stores received write data number information 4 indicating the number of data to be received at the start of a write operation as a write data number set signal 5, and receives received write data that is sequentially sent. Count the number set signal 13. If the same number of received write data set signals 13 as the write data number information 7 have not been received at the end of the write operation, the host device abnormality signal 8 is activated. The ECC data inversion instruction circuit 2 monitors the completion of receiving the number of received write & data set signals 13 equal to the write data number information 7, outputs the ECC data selection signal 10, and at the same time outputs the host device abnormality signal. If 8 occurs, E is generated at the timing of the last byte of ECC.
A CC data inversion instruction signal 11 is output. At this time, the write command signal 9 remains active from the rise of the received write command signal 6 until the writing of the ECC is completed.

Further, the clock 16 is used to detect the timing of EOC writing.

The write data editing circuit 3 receives the ECC data selection signal 10.
is inactive, the received write data 12 is temporarily stored using the received write data set signal 13.
When the ECC data selection signal IO becomes active, the EC
C data 14 is temporarily stored using an ECC data set signal 15, and the data is output as write data 17. However, if the ECC data inversion instruction signal 11 becomes active at this time, the polarity of the ECC at that time is inverted.

FIG. 2 is a circuit diagram showing details of the host device abnormality detection circuit 1. As shown in FIG. At the start of the write operation, the received write data number information 4 is stored in the register 71 as the write data number information 7 in response to the write data number set signal 5. Subsequently, the received write data set signals 13 that are sequentially sent are connected to the clock terminal of the counter 22, and the number thereof is counted and output as a write data set number signal 27. In addition, counter 2
Since the received write command signal 6 is connected to the reset terminal through the inverter 24, it works only while the received write command signal 6 is active. The write data number information 7 and the write data set number signal 27 are compared by a comparator 23 and connected to a D type flip-flop 26 through an inverter 25. Furthermore, since the received write command signal 6 is connected to the clock terminal of the D type flip-flop 26 through the inverter 24, when the received write command signal 6 becomes inactive, the write data number information 7 and the write data set number signal 27 are If they do not match, the D type flip-flop 26 is set and the host device abnormality signal 8 is output.

FIG. 3 is a circuit diagram showing details of the ECC data inversion instruction circuit 2. The received write command signal 6 is connected to a clock terminal of a D-type flip-flop 33, which outputs a write command signal 9 at the start of a write operation. During the write operation, the received write color data set signal 13 is counted by the counter 31 and compared with the write data number information 7 by the comparator 32, and the completion of reception of the received write data set signal 13 is monitored. The D-type flip-flops a and y 35, which are connected to the set terminal through the inverter 34 for the write command signal 9,
It is set at the start of a write operation, and the data transfer incomplete signal 51 is active, but becomes inactive when the counter 31 matches the write data number information 7. Therefore, the anti-game I 42 changes to "0" and at the same time the counter 38 starts counting the output of the AND gate 42 and the write command signal 9 The ECC data selection signal 10, which is ANDed with , becomes active.

Constant (1) for which the counter 38 outputs the required ECC transfer length
When equal to the output signal of circuit 36, comparator 39
The type flip-flop 33 is reset and the write command signal 9 becomes "θ". Also, when receiving the host device abnormality signal 8, the 7nd gate 42 is connected through the inverter 41.
The output of will change to 0'' and begin the ECC write operation.

However, in this case, the data transfer incomplete signal 51 remains active, so the counter 38 becomes equal to the output signal of the constant (2) circuit 37, which outputs a value 1 byte less than the required transfer length. At this time, the output of the comparator 40 sets the flip-flop 44 through the AND gate 43, and the ECC data inversion instruction signal 11 becomes active.

The ECC data selection signal 10 and the ECC data inversion instruction signal 11 become "0" together with the write instruction signal 9 when a predetermined ECC transfer is completed.

FIG. 4 is a circuit diagram showing details of the write data editing circuit 3. Received write data 12 is received write data fi
It is temporarily stored in the register 71 by the fi1 set signal 13,
It is input to the selection circuit 75. Further, the ECC data 14 is also temporarily stored in the register 72 using the ECC data set signal 15, and is input to the selection circuit 74. At the same time, the output of the register 72 is input to the selection circuit 74 after passing through the polarity inversion circuit 73, and the output of the selection circuit 74 is input to the selection circuit 74.
5 is input. Since the selection circuit 74 and the selection circuit 75 are connected with the ECC data inversion instruction signal 11 and the ECC data selection signal 10 as selection switching signals, respectively, the write data 17 is written while the ECC data selection signal 10 is inactive. is the output of the register 71, and becomes the output of the register 72 when the ECC data selection signal lO becomes active. However, when the ECC data inversion instruction signal 11 becomes active at this time, the polarity of the ECC at that time becomes inverted.

FIG. 5 shows the data format on the medium during normal writing and the data format on the medium when writing is interrupted according to this embodiment.

The upper side is the data format on the medium due to normal writing,
It shows that EC01 to ECC6 are written in the original positions for data 1 to data N. On the other hand, the lower part is the data format on the medium when writing was interrupted, and data 1
This shows that ECC1 to ECC6 are added to data M (M is the number of data that had already been written until the time of interruption), and that the polarity of ECC6 is inverted.

〔Effect of the invention〕

As explained in detail above, in the data storage control device of the present invention, during a write command operation from a host device, the write command is interrupted before receiving a received write data set signal equal to the number of write data due to an abnormality in the host device. is detected, the write operation is interrupted, and ECC writing is started. At this time, only the number of data within the correction capacity of the ECC is written with the polarity reversed, so this data portion cannot be read later. Even if a read error is determined by the ECC in this case, if a correction operation is performed, the correction position and correction pattern will make it easy to recognize that the read error is due to an interruption in the write operation of the host device, and take appropriate measures. A data storage control device is obtained that can perform the following operations.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram showing one embodiment of the present invention, Fig. 2 is a circuit diagram showing details of a detection circuit for a host device or higher, and Fig. 3 is an E
FIG. 4 is a circuit diagram showing details of the CC data inversion instruction circuit, FIG. 4 is a circuit diagram showing details of the write data editing circuit, and FIG. FIG. 3 is a diagram showing a data format on a medium. ■・・・Host device abnormality detection circuit, 2・・・・・・
ECC data inversion instruction circuit, 3...Write data editing circuit, 4...Received write data number information,
5...Write data number set signal, 6...
... Received write command signal, 7 ... Write data number information, 8 ... Upper device abnormality signal, 9 ...
...Write command signal, 10...ECC data selection signal, 11...ECC data inversion instruction signal,
12... Received write data, 13...
Receive write data set signal, 14...ECC
Data, 15... ECC data set signal, 1
6...Clock, 17...Write data. Agent Patent Attorney Uchihara Oto If the number of times is 3 and Figure 4 is 2M Digital: Is there a lot of money? q=(Σ
・] Fukuchi [W 浬 1 Spell H ``l Shiki Degu 5 fig.

Claims (1)

[Scope of Claims] In a data storage control device that receives the number of write data in advance from a host device and subsequently receives the write data in synchronization with a write data set signal and sends it to a data storage device, Store the received write data number information in the write data number set signal and output it as the write data number information.At the same time, count the received write data set signals and before receiving the same number of received write data set signals as the received write data number information. When the host device abnormality detection circuit detects that the write operation has been interrupted, and the receive write command signal that instructs data writing becomes active, the host device starts monitoring whether the received write data set signal matches the write data count information. If the device abnormality detection circuit occurs, the ECC data selection signal is activated to terminate the write operation immediately.
(error collection code) starts writing,
Moreover, to indicate that a write abort operation has occurred, the ECC
an ECC data inversion instruction circuit that outputs an ECC data inversion instruction signal instructing to invert the polarity of only the number of data within the correction capability of the controller; The write information temporarily accumulated with the signal is used as write data, and while the ECC data selection signal is active and the ECC data inversion instruction signal is inactive, the ECC data is set as write data, and the ECC information temporarily accumulated with the ECC data set signal is used as write data. And if the ECC data selection signal is active and the EC
A data storage control device comprising: a write data editing circuit that outputs ECC information with polarity inverted as write data when a C data inversion instruction signal also becomes active at the same time.