JP2536907B2 - Diagnostic circuit having operation guarantee circuit - Google Patents

Description

The present invention relates to a diagnostic circuit for testing the normality of the operation of a logic circuit provided together with a general logic circuit such as an integrated circuit, and the diagnostic circuit itself fails to affect normal operation. For the purpose of providing a means capable of preventing the application and detecting the occurrence of a failure in the diagnostic circuit, for example, a signal that is always "1" during system operation and always "0" during circuit diagnostic operation. , Means for giving a signal that is the logical sum of the system reset signal as a reset input of all the diagnostic path activating flip-flops, and means for obtaining the logical sum of the outputs of all the diagnostic path activating flip-flops. It is configured by providing.

[Field of Industrial Application] The present invention provides a diagnostic path activation flip-flop that can be set / reset asynchronously with an ordinary circuit that constitutes a logic circuit in an integrated circuit or the like, By setting a specific value in the diagnostic path activating flip-flop, the flip-flop circuit of the normal circuit can be controlled to activate the path between the specific flip-flops. It also relates to prevention of malfunction of the diagnostic circuit and detection means when the diagnostic circuit itself has a failure.

[Prior Art] When manufacturing an integrated circuit, it is required to perform a test on the integrated circuit alone at the manufacturing stage to prevent defective products from being shipped.

However, since the degree of integration of integrated circuits has increased in recent years, it is not easy to carry out the test.

Therefore, a diagnostic circuit is provided separately from a normal circuit in the integrated circuit to set or read arbitrary data in a flip-flop (hereinafter also referred to as a latch) in the logic circuit, or to perform flip-flop operation. A specific path between them is activated to check whether or not the data is normally transferred, and further check the transfer time.

To further explain such a diagnostic circuit,
In an integrated circuit, etc., when a circuit does not operate normally due to a failure of any logic element in the logic circuit, etc.
A scan-in / scan-out circuit is provided.

This is to provide a gate for configuring a circuit for testing separately from a circuit for performing normal logic operation.
For example, by the gate, each flip-flop is connected in series, data is input from the first flip-flop,
Each clock is sequentially transferred to each flip-flop connected in series to set arbitrary data in each flip-flop, and by sequentially reading data from the last flip-flop, the internal flip-flop is read. It is intended to confirm the operation and normality of the group.

Further, as such a test circuit, a circuit that enables setting of arbitrary data in the flip-flop and reading of data by designating an address of each flip-flop is also used.

By using such a function, it is possible to confirm the data transfer between the identified flip-flops and the transfer time.

For example, in the logic circuit configured as shown in FIG. 2, when the data transfer from the flip-flop 50 to the flip-flop 51 is to be checked, the AND gate 56
Each of ~ 58 must satisfy the AND condition, and for that, the AND condition of the AND gate 59 must be satisfied.

In order to satisfy these conditions, the flip-flops 52 to 55 need to be set to "1".

Therefore, by setting the flip-flops 52 to 55 “1” by the scan-in operation described above and then stopping the clock (CLK) of these flip-flops 52 to 55,
The path between the flip-flop 50 and the flip-flop 51 can be activated.

As a result, the flip-flop 50 and the flip-flop 51
Measurement of data transfer between and can be performed.

The clock control of these flip-flops is performed by setting a specific value in the diagnostic path activating flip-flop.

FIG. 3 is a diagram for explaining such a diagnostic path activating circuit, wherein 60 and 61 are diagnostic path activating latches, and 6
2 to 66 are combinational circuits, 67 and 68 are AND circuits, 69 to 71 are general logic circuit latches, 72 is a diagnostic path activation circuit, and 73 is a general logic circuit.

In the figure, when "0" is set in the diagnostic path activating latch 60 and the internal output of the combinational circuit 62 is "1",
When “0” is applied to the clock enable terminal of the latch 69 and the latch 69 is in the clock enable state, when “1” is set to the diagnostic path activation latch 60, the latch 69 is activated.
Enters the clock inhibit state.

[Problems to be Solved by the Invention] The above-mentioned diagnostic path activating latch should not operate during normal operation and is used only during circuit diagnosis. When input, the clock is enabled,
The data can be set.

Then, during the system operation, the latch of the general logic circuit continues to hold the value that enables the clock enable state.

However, if the value of these diagnostic path activation latches is inverted for some reason, the general circuit will malfunction, while it is extremely difficult to find the cause because it is a failure of the diagnostic circuit. There was a problem that there was.

In view of such conventional problems, the present invention does not easily invert the value of the diagnostic path activation latch, and when such a situation occurs, it can be detected immediately. It is intended to provide a circuit system.

[Means for Solving the Problems] According to the present invention, the above-mentioned object is achieved by the means described in the claims. That is, the present invention is
A diagnostic path activation flip-flop circuit that can be set or reset asynchronously with a flip-flop circuit that configures the logic circuit, and that controls the clock of the flip-flop that configures the logic circuit by the setting or resetting; By setting a specific value in the diagnostic path activating flip-flop circuit, an input of the gate is provided in order to activate a gate existing between specific flip-flop circuits of the flip-flop circuits forming the logic circuit. In a diagnostic circuit capable of activating a path between the specific flip-flop circuits by controlling a clock of a flip-flop circuit forming the logic circuit connected to the Polarity for resetting the diagnostic path activation flip-flop circuit During the logic circuit diagnosing operation, a signal having a polarity opposite to that of the signal of the polarity that is always reset and a system reset signal for resetting all of the logic circuit and the diagnostic circuit are ORed. And means for providing all the ORed signals as reset inputs to all the diagnostic path activating flip-flop circuits, and means for obtaining the logical sum of all outputs of the diagnostic path activating flip-flop circuits. Is a diagnostic circuit characterized by being provided with an operation guarantee circuit.

[Operation] In the diagnostic circuit having the operation guarantee circuit configured as described above, the diagnostic path activation flip-flop is
It is reset by the system reset signal, and thereafter, the reset state is forcibly continued by continuously applying the signal of the polarity for resetting the flip-flop to the reset terminal of the flip-flop. Therefore, it is possible to avoid a situation where the polarity of the diagnostic path activating flip-flop is inverted when it is not intended due to induction or pulse noise, and a stable circuit operation can be expected.

In the unlikely event that the diagnostic path activation flip-flops are set to the set state irrespective of the input due to a hardware failure or the like, the circuit for obtaining the logical sum of the outputs of all the diagnostic path activation flip-flops This can be easily detected from the output.

[Embodiment] FIG. 1 is a block diagram of an embodiment of the present invention.
The gate, 2 diagnostic path activation condition setting circuit, 3 ₁ -
Reference numeral 3n represents a diagnostic path activating latch, and 4 represents an OR gate.

In the figure, at the time of diagnosis, a set signal is applied to the set terminals (S) of the diagnostic path activation latches 3 _{1 to} 3n according to the conditions set in the diagnostic path activation condition setting circuit 2 to set the latches. Its output controls the clock of the general latch to form the necessary diagnostic path.

On the other hand, during normal operation, the diagnostic path activation latch
3 ₁ 3n, the output of the OR gate 1 is reset is applied to the reset terminal (R). A system reset signal and a diagnostic path activating latch reset signal are applied as inputs to the OR gate 1.

Of these signals, the system reset signal is given as a pulse signal, but the diagnostic path activation latch reset signal is always given as "1" without changing its polarity (in this case, "1") Latch for path activation 3 ₁
Force ~ 3n to be reset.

Further, each output of the diagnostic path activating latches 3 _{1 to} 3n is input to the OR gate 4, and any _one of the diagnostic path activating latches 3 _{1 to} 3n is in the set state even though the output is not in the diagnostic state. When this occurs, a diagnostic path activation latch error signal is output.

[Effects of the Invention] As described above, according to the present invention, it is possible to set or reset asynchronously with a flip-flop circuit forming a logic circuit, and the flip-flop forming the logic circuit can be set or reset. A flip-flop circuit for activating a diagnostic path for controlling the clock, and a specific flip-flop circuit among the flip-flop circuits constituting the logic circuit by setting a specific value in the diagnostic-path activation flip-flop circuit. Controlling a clock of a flip-flop circuit constituting the logic circuit connected to an input of the gate to activate a gate existing therebetween, thereby activating a path between the specific flip-flop circuits. In the diagnostic circuit that enables The operation has an advantage that the influence on the general circuit can be greatly reduced and a stable operation of the general circuit can be expected.

Further, since the malfunction due to the hardware failure of the diagnostic path activating flip-flop can be detected promptly, the systematic measure can be carried out quickly and easily, so that the reliability of the circuit operation can be improved. is there.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an example of a logic circuit, and FIG. 3 is a diagram explaining a diagnostic path activating circuit. 1,4 ... OR gate, 2 ... Diagnostic path activation condition setting circuit, 3 _{1 to} 3n ...... Diagnostic path activation latch

Claims (1)

(57) [Claims] 1. A flip-flop for diagnosing a path, which can be set or reset asynchronously with a flip-flop circuit forming a logic circuit, and controls the clock of a flip-flop forming the logic circuit by the setting or resetting. Circuit for activating a gate existing between specific flip-flop circuits of the flip-flop circuits forming the logic circuit by setting a specific value in the diagnostic path activating flip-flop circuit. A diagnostic circuit capable of activating a path between the specific flip-flop circuits by controlling a clock of a flip-flop circuit forming the logic circuit connected to the input of the gate, wherein the logic circuit During operation, the diagnostic path activation flip-flop circuit is always reset. Signal having a polarity opposite to the polarity signal which is always reset during the logic circuit diagnostic operation, and a system reset signal for resetting all of the logic circuit and the diagnostic circuit. Means for giving a logical sum of the signals as the reset input of all the diagnostic path activating flip-flop circuits, and the logic of all outputs of the diagnostic path activating flip-flop circuits A diagnostic circuit comprising a means for obtaining the sum and an operation guarantee circuit including the means.