JPS5812192A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To ensure a free application to all flip-flops, by securing the reading/writing to a logical storage circuit like a flip-flop, etc. within an LSI from the outside of the LSI, even though circuit is under working. CONSTITUTION:A flip-flop 1 in a circuit is formed with a series 54 of a simultaneous access memory and connected to an input 7, an output 8, a set terminal 13 and a reset terminal 14 respectively. On the other hand, an address 11 that selects a prescribed flip-flop is decoded by an address decoder 53 and connected to a series 55 of the other side of the simultaneous access memory via a read/write decoder 52. Thus the write and reading is possible freely from outside. Furthermore the constitution of a simultaneous access memory is simplified with a big reduction of numbers of external pins owing to the use of a C-MOS master slice LSI.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to an LSI (
This invention relates to an additional circuit inside an LSI for electrically diagnosing a large-scale integrated circuit (large-scale integrated circuit) from outside the LSI.

As LSIs become more highly integrated and functional, operation evaluations are needed to ensure their reliability and to investigate the causes of defects.
There is a growing need to perform post-manufacturing diagnostics such as delay measurement, failure analysis, and failure diagnosis quickly and at low cost. wife! D.LS
Since the number of external output pins in I is limited due to the package, only a portion of the LSI's internal circuit status can be directly sensed. Therefore, in order to determine whether or not an LSI is normal, the more complex the function, the more procedures are required. There are cases where activation cannot be achieved using the original activation method.

The conventional technology for these is as shown in FIG. 1, the set terminal 13, reset terminal 14,
The output 8 has a set gate 2, a reset gate 3, and a read gate 4, respectively, and a decoder 5 decodes an address 11 for selecting a desired seven lip-flops and a control signal 10 for instructing read/write. One that controls the gates 2, 3.4 and reads/writes to the flip-flop 1, and as shown in FIG. 2, a shift register without the decoder 5 like the circuit shown in FIG. There is a method of reading and writing the contents of flip-flop 1 through 21.

7 is an input terminal, 9 is a set/reset terminal, 12 is a read/data terminal, 22 is a shift register input data terminal, 23 is a shift pulse signal terminal, 24 is a load signal terminal, 25 is a store signal terminal Terminal 26 is a terminal for shift register output data. Since the present invention is close to the former, an example of the former realized by a C-MO8 circuit is specifically shown in a circuit diagram as shown in FIG. This circuit is AND
Gate 32, NOR gate 33, inverter 31, P-
The loop of the MOS) transfer gate 34 constitutes a D-type latch with set and reset terminals. In order to access this D-type latch from the outside, a Lebel pledge gate 36.0 level write gate 37 is provided at the set and reset terminals to specify the state of the latch, and the output is also output to the read gate 38. However, it is very inconvenient as it requires many gates and requires changes in design depending on the type of flip-flop, and the method using a shift register has a problem with circuit operation. The drawback was that the inside could not be accessed.

34 is an N-MOS) transfer gate, 39 is an internal write control terminal, 40 is an internal write data terminal, 41
is an internal output terminal, 42 is a set input terminal, 42 is a set input terminal, 43 is a reset input terminal, 44 is a level write control terminal, 45 is a θ level write control terminal, 46 is a read control terminal , 47 is a read data terminal, 48 is an external write addition circuit, and 49 is an external read addition circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a diagnostic circuit system that allows reading and writing to logic storage circuits such as 7 flip-flops inside an LSI from outside the LSI even during circuit operation, and is applicable to all types of flip-flops.

The present invention achieves the above object by configuring a logic storage circuit such as a flip-flop inside an LSI using a temporary storage element (simultaneous access memory) that allows reading and writing from two systems at the same time. It is.

Next, one embodiment of the present invention will be described with reference to the drawings.

To explain Fig. 4, flip 70 in the circuit
7" 11d is configured using a series 54 of simultaneous access memory (7) and is connected to the input cuff, output 8, set terminal 13, and reset terminal 14. On the other hand,
Address 11 for selecting a predetermined flip/70 knob
is decoded by the address decoder 53 and connected to another series 55 of simultaneous access memory via the read/write decoder 52, and is
Reading can be performed freely. 51 is a data line. In this example, no special additional circuit is required other than the decoder, and there is almost no burden on the designer.

Now, the problems in implementing the present invention are as follows.
The problem is how to easily configure a simultaneous access memory, and how to reduce the number of input/output pins required to the outside of the LSI in order to write to and read from flip-flops inside the LSI.

However, the present invention can solve all of the above problems in a C-MOS master slice LSI with built-in memory. That is, in the C-MO8 circuit, the former problem can be solved by constructing a simultaneous access memory with a simple circuit as shown in FIG. To explain Fig. 5, the inverter 61 is connected in a loop with a P-MOS transfer gate 63, and an N-MOS (N-MOS) is connected at each connection point.
A transfer gate 62 is connected to input and output data. In addition, since the LSI of this embodiment has a built-in memory, the address lines that already exist are used, and a part of the memory address space is applied to the simultaneous access memory in the 7 lip-flops, thereby significantly reducing the number of external pins for diagnosis. The latter problem is also solved. In the figure,
64 is a first write data terminal, 65 is a first write permission signal terminal, 66 is a first read data terminal, 67 is a first read permission signal terminal, 68 is a second read permission signal terminal, and 69 is a second read permission signal terminal. A second read data terminal 70 is a second write permission signal terminal, and 71 is a second write data terminal.

Now, in order to clarify the effect of the present invention, C
A comparison will be made between the additional circuit shown in FIG. 3 for externally accessing the D-type level trigger latch in the MO8 circuit and an example in which the present invention is implemented in a C-MO8 circuit to achieve a similar function.

An example in which the present invention is implemented is shown in FIG.
O8) Lancer gate 86, inverter 31,
Set at transfer gate 84 for internal swearing.
It constitutes a D-type latch with a reset terminal. Both ends of the P-MOS transfer gate 86 for external writing are connected to external input/output data via the N-MO8 transfer gate 87°88 for external input/output.
Even when the D-latch is in operation, it can be accessed from the outside, and the circuit is simplified compared to the conventional system shown in FIG. In the figure, 85 is an N-MOS) transfer gate, 89 is an internal write control terminal, 90 is an internal write data terminal, 93 is an external input/output data terminal, 9
4 is an external write control terminal, and 95 is an external read control terminal.

The effects of this embodiment can be summarized as follows.

(1) The number of required parts is reduced compared to the conventional method.

(2) It can be used with any type of 9-logic storage circuit such as a flip-flop, and there is no need for set/reset terminals to be provided.

(3) Logic design can be performed without requiring a special burden on the designer.

(4) Since there is no need to pass a gate to the input of a slip-flop, etc., gate delays caused by this can be avoided.

(If a part of the memory space in the 51' LSI is used, no special diagnostic output pin is required, and the internal flip-flops can be accessed in the same way as general memory.

(6) Since signals generated inside the LSI can be monitored, advanced usage can be established without being restricted by external pins.

FIG. 7 shows an example in which the present invention is applied to a shift register.
This shows that it is possible to easily access shift registers without set/reset terminals, which was difficult with the prior art. To explain Fig. 7, N-
MOS) transfer gate 62, P-MOS) transfer gate 63, C-, and MOS inverter 61 are constructed in the same manner as the 1-bit D-type latch, but the D-type latch incorporates simultaneous access memory. connection,
It constitutes a 1-bit shift register.

In the figure, 104 is a terminal for shift pulses, 1o5 is a terminal for inverting shift pulses, 106 is a terminal for internal data, 1o7 is a terminal for external type output data, 108 is a terminal for external read permission signal, and 1o9 is a terminal for external read permission signal. This is a terminal for external write permission signals.

Furthermore, in the examples so far, external input/output data is shared for writing and reading, but there is no problem in writing and reading them separately.

FIG. 8 shows another configuration of concurrent access memory. C-MO8NAND Game) 110t-Used in place of the inverter 61 in FIG. 5, and has a set terminal 112 and a reset terminal 111 inside.

Figure 9 shows an LSI diagnostic circuit using simultaneous access memory applied to RAM, which uses advanced signals to issue new commands while externally monitoring information generated internally and stored in RAM in real time. This is an example of processing. To explain the diagram, the processor 2 inside the LSI 201
In this system, signals generated by 02 and stored in simultaneous access memory 203 are accessed by external circuit 204 to give new instructions to processor 202.

According to the present invention, logic storage circuits such as flip-flops inside an LSI can be easily accessed from outside the LSI.

[Brief explanation of drawings]

1 and 2 are block diagrams for explaining the prior art, FIG. 3 is a circuit diagram specifically showing FIG. 1, and FIG. 4 is a block diagram showing an embodiment of the present invention. 5 is a circuit diagram showing a simultaneous access memory according to another embodiment of the present invention;
9 to 9 are circuit diagrams showing still other embodiments of the present invention. l...Flip flop, 52 read write
Decoder, 53...Address decoder, 54°55.
...Simultaneous access pemori. 1 sen 13, 2nd closed/3 3rd eye (l calculation 4 closed 5th figure 6 round l #'7 closed 108/θ9 3rd δl pierced 91 +" io / O4

Claims (1)

[Claims] 1. A semiconductor integrated circuit comprising a logic memory circuit such as a flip-flop, which is constructed using a temporary memory element that allows reading from two base columns at the same time. Integrated circuit device.