JPS6111803Y2 - - Google Patents

Description

[Detailed explanation of the idea]

This invention relates to a memory device, and more particularly to a memory device that allows read or write operations to be performed simultaneously at different speeds. In conventional memory devices, when performing read or write operations at different speeds, it is possible to perform them serially in time or to interrupt a high speed operation with a low speed operation. However, if they are performed serially in time, the high-speed and low-speed operations will be intermittent, and if the low-speed operation is interrupted during the high-speed operation, the high-speed operation will occur during the period of the low-speed operation. The problem was that the system was interrupted or lost.
For example, if we consider the field memory of a TV as this memory and transmit it at low speed while displaying it on the monitor, we can use the high-speed (standard TV rate)
While repeatedly reading data, low-speed reading is simultaneously performed for transmission. In this case, low-speed data for transmission will be mixed into the high-speed data (monitor signal), resulting in noise.
Of course, a low-speed timing meter can be detected, and the low-speed data mixed in with the high-speed data can be set to 0 or 1, but in this case, the monitor image becomes a black dot or a white dot, making the image difficult to see. This idea was made in view of these points, and aims to provide a memory device that can obtain normal data for both high-speed and low-speed data even when high-speed reading and low-speed reading or writing are performed at the same time. purpose. Figure 1 is a diagram showing the configuration of a conventional memory device, where 1 is a memory, 2 is a low-speed address counter,
3 is a high-speed address counter, 4 is an address selector for switching between high-speed and low-speed addresses,
5 is a latch circuit for low-speed data, 6 is a latch circuit for high-speed data, 7 is a low-speed clock input terminal, 8 is a high-speed clock input terminal, 9 is a low-speed data output terminal, and 10 is a high-speed data output terminal. The operation is as follows. Now, if we consider the case where a low-speed clock is input only to input terminal 7 and no high-speed clock is input to input terminal 8, the low-speed address counter 2 changes due to the low-speed clock, the address is selected by address selector 4, and the memory Low speed data is sequentially read out from 1 and latched by the latch circuit 5 for low speed data, and the low speed data is obtained at the output terminal 9. Conversely, if the low-speed clock is not input to the input terminal 7 and the high-speed clock is input only to the input terminal 8, the high-speed address counter 3 will similarly change due to the high-speed clock, and the address will be changed by the address selector 4. The selected high-speed data are sequentially read out from the memory 1, latched by the high-speed data latch circuit 6, and the high-speed data is obtained at the output terminal 10. When high-speed operation and low-speed operation are to be performed simultaneously, a low-speed clock is input to input terminal 7, and a high-speed clock is input to input terminal 8 at the same time. In this case, the above-mentioned high-speed operation is performed during the period when there is no low-speed clock, and when a low-speed clock occurs, the address selector 4 selects the address of the low-speed address counter, and the above-mentioned low-speed operation is performed. The above-mentioned normal low-speed data can be obtained from the low-speed data output terminal 9, but the high-speed data output terminal 10
The signal obtained at this time is a signal in which low-speed data from a low-speed clock is mixed into high-speed data. Figure 3 shows this situation. In the figure, a is a high speed clock and b is a low speed clock. In general, the period of the slow clock is not necessarily an integer multiple of the period of the fast clock, and the timing of the slow clock does not overlap with the timing of the fast clock, but it is easy to reset the timing of the slow clock to the timing of the fast clock. Assume that the input terminals 7 and 8 in FIG. 1 are supplied with a clock in which the timing of the low-speed clock b matches the timing of the high-speed clock a, as shown in FIG. 3. Figure 3c shows the original high speed data. That is, when only the low speed clock a is used, data corresponding to the addresses can be obtained sequentially in this way. However, as shown in Figure 3, the high speed clock and low speed clock are input at the same time, and the low speed clock is input at the timing of high speed clock n+1.
When M ₁ arrives, the output of memory 1 becomes data at address M ₁ by the low-speed clock, which is latched by latch circuits 5 and 6, and the high-speed data d at output terminal 10 and the data at output terminal 9 as shown in FIG. Both low-speed data e become low-speed data at address _M1 . That is, at the original location n+1 of high-speed data d,
Low speed data _M1 will be mixed in. Similarly,
Even when low-speed clock _M2 comes at the timing of high-speed clock n+k+1, the original n+k of high-speed data d
Low-speed data M ₂ is mixed into the +1 location. The low-speed data mixed into the high-speed data becomes noise for the high-speed data. FIG. 2 is a diagram showing the configuration of a memory device according to this invention, in which 11 is a data delay selection circuit, 12 is a gate circuit for gating a high-speed clock signal during low-speed clock and stopping the high-speed address counter 3, and 13 is a data delay selection circuit. This is a clear signal input terminal for returning the delay selection circuit 11 to its initial state. The operation of this device is generally as follows. Now, it is assumed that the low-speed clock comes n times during one operation cycle. First, before starting the operation, a clear signal is input to the input terminal 13, and the data delay selection circuit 11 is set to the initial state (N
Bit delay output, N≧n). After inputting the clear signal, only high-speed operation is performed as in the conventional device until a low-speed clock arrives. However, the high-speed data obtained at the high-speed data output terminal 10 is delayed by N bits compared to the conventional device. Next, when a low-speed clock arrives, low-speed operation occurs, but at this time the gate circuit 12 operates, stops the high-speed address counter 3, and advances the delay time of the data delay selection circuit 11 by one bit. For example, as shown in FIG. 4, if the low-speed clock M1 arrives at the timing of the high-speed clock n+ ₁ from the initial state (2-bit delayed output), the high-speed clock n+1 will be output from the gate circuit 1.
2, and the high speed address counter 3 is stopped at n. In addition, the data delay selection circuit 1
The output of 1 switches from the 2-bit delayed output shown in FIG. 3(e) to the 1-bit delayed output shown in FIG. At this time, the 2-bit delay output has
_M1 is output, but n+ is output as 1-bit delay output.
1 is output, so high-speed data output terminal 1
0, continuous high-speed data of n and n+1 is obtained as shown in FIG. That is, the above _M1 is removed. Next, when the low speed clock _M2 comes at the timing of the high speed clock n+k+1, similarly,
The high speed clock n+k+1 is gated by the gate circuit 12, the high speed address counter 3 is stopped at n+k, and the output of the data delay selection circuit 11 is as shown in FIG.
After one high-speed clock cycle, the 1-bit delayed output shown in FIG. When the operation of one operation cycle is thus completed, the data delay selection circuit 11 is reset to the initial state, and the same operation is performed again in the next cycle. For example, when this idea is applied to a CRT, if it is reset every horizontal scan, the number of low-speed clocks that occur during that scan period will be extremely small, 1 to 2 times, and therefore unnecessary data will not be generated. Since the number of bits is small, the number of bits of the shift register constituting the data delay selection circuit can also be small. In this way, in the device according to this invention, even if low-speed and high-speed operations are performed simultaneously, continuous normal data with a total delay of N bits can be obtained from the low-speed output data as well as the high-speed data. FIG. 5 is a diagram showing the configuration of the data delay selection circuit 11, which is a component of this invention, where 14 is an N-bit shift register, and 15 is an input/output signal of the N-bit shift register 14 (0 to N-bit delayed output). A data selector 16 is a timing counter for selecting one of them. timing counter 16
The output becomes N due to the clear signal from the input terminal 13, and the low-speed clock after the clear signal causes the output to become N.
As shown in Table 1, the output is delayed by a certain high-speed clock period from the low-speed clock timing by N-1,
N-2, . . . 0, and the output of the timing counter 16 operates the data selector 15 to switch the delay output as described above.

【table】

[Table] FIG. 6 is a diagram showing one specific example of the configuration of the timing counter 16, in which 17 is a subtraction counter, and 18 and 19 are M-adic (M≧N) addition counters. In this timing counter 16, the subtraction counter 17 is loaded to N by a clear signal from the input terminal 13, and the addition counter 19 is loaded with the output of the addition counter 19 by the low-speed clock from the input terminal 7, and the output of the addition counter 19 is loaded by the input terminal 7. 8 and outputs a carry signal, which is applied as a clock signal to the subtraction counter 17. Since the output of the addition counter 19 loaded into the addition counter 18 changes depending on the number of low-speed clocks after the clear signal, the time when the carry signal of the addition counter 18 is delayed from the low-speed clock is within the high-speed clock period N~1. Change. That is, the output of the timing counter 16 (output of the subtraction counter 17) changes as shown in Table 1. In the above description, the number of low-speed clocks in one operating cycle was assumed to be n=N, but it is clear that the same device can operate without any problem if it is nN. As mentioned above, according to the memory device according to this invention, even if high-speed reading and low-speed reading or writing are performed simultaneously, normal data can be obtained for both high-speed and low-speed data, and the effect is great. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a memory device that performs high-speed and low-speed operations, FIG. 2 is a block diagram showing an embodiment of the memory device according to this invention, and FIG.
The figure is an explanatory diagram for explaining the operation of a conventional memory device, FIG. 4 is an explanatory diagram for explaining the operation of the memory device according to this invention, and FIG. 5 is an explanatory diagram for explaining the operation of the memory device according to this invention. FIG. 6 is a block diagram showing an example of a delay selection circuit. FIG. 6 is a block diagram showing an example of a timing counter which is an element of the data delay selection circuit. In the figure, 1 is a memory, 2 is a low-speed address counter, 3 is a high-speed address counter, 4 is an address selector, 5 and 6 are latch circuits, 7, 8 and 13 are input terminals, 9 and 10 are output terminals, and 11 is data Delay selection circuit, 12 is a gate circuit, 14 is a shift register, 15 is a data selector, 16 is a timing counter, 17 is a subtraction counter, 18
and 19 are addition counters. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] A low-speed address counter that counts low-speed clocks, a high-speed address counter that counts high-speed clocks, a memory accessed by both address counters, and a gate circuit that gates the high-speed clock and stops the high-speed address counter when the low-speed clock is active. , a first latch circuit that latches the memory output with the low-speed clock, a second latch circuit that latches the memory output with the high-speed clock, and the output of the second latch circuit is set to N bits in the initial state. a data delay selection circuit which delays the output of the second latch circuit by shortening the delay time to (N-n) bits according to the number n of low-speed clocks in the number of high-speed clocks at the time of the low-speed clock; Memory device with.