JPS61155876A - Diagnozing method of integrated circuit - Google Patents

Abstract

PURPOSE:To improve the efficiency of diagnosing operation by writing data showing a test mode in normal external access in a storage circuit provided in an integrated circuit, and setting a desired test mode among plural kinds in the integrated circuit without providing any test terminal. CONSTITUTION:This system is equipped with the integrated circuit 10 which has logical circuits internally and has input terminals for an address and data for the access of a processor, and the integrated circuit 10 is provided with the storage circuit (register) 22 where data showing a test mode is set through an input terminal. When a diagnosis is taken, the data indicating the test mode is set in the register 22 through the input terminal from an external diagnosing device and respective outputs of the internal logical circuit group. Further, the register is held reset all the time in normal operation where access is attained by a processor 30.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for diagnosing integrated circuits such as L81, and in particular, a method for specifying a test mode F without adding an input terminal for specifying a test mode in an integrated circuit. This invention relates to a method for diagnosing integrated circuits.

An integrated circuit such as L8I is a package of a logic circuit group consisting of a large number of logic gate elements, and is treated as one closed circuit (black box) with a certain unit of logic function and data processing function. On the other hand, in order to test (diagnose) the functions of this integrated circuit, it is necessary to configure it so that the outputs of each part of the built-in logic circuit group can be directly obtained. However, on the other hand, there is also a strong desire to avoid adding special input/output terminals for testing to integrated circuits.

[Conventional technology]

Conventionally, for example, a diagnostic method as shown in the second rgJK has been used.

In FIG. 2, 10 is a circuit to be diagnosed, which is a packaged integrated circuit such as an LSI. 11 to 19 are a group of logic circuits built into the integrated circuit IO. In the example shown in the figure, the multi-connected counter elements 11-0.11-1.・
...The counter section 11 consisting of 11-1, the parity checker consisting of multiple gates, and 70 tubes 13.
Reset circuit 14. And gate 15, 16. Orgate 17, 19. and each logic circuit such as an inverter 18.

Further, in FIG. 2, the signal line extending from the left side of the integrated circuit "$10" indicates the input signal line to the circuit 10. Furthermore, the signal line extending to the right side of the circuit 10 indicates the output signal line. Corresponding to each of the output signal lines, the circuit 10:
Needless to say, input/output terminals are provided.

Therefore, in addition to the operation clock CLK, the counter section 11 has counter elements 11 . A test signal TESTl is supplied that forces . . . to operate.

This test signal THAT1 becomes the input power of the counter element via the OR game 19. From this, it becomes possible to obtain the outputs CTo, . . . CTn of the counter elements of each stage all at once.

On the other hand, the parity checker 12 normally uses a CPU.

It is configured such that data DATA from a memory or the like is supplied, and when a parity error occurs, an error signal FXRR is outputted as an interrupt signal NMt via the flip 70 knob 13. When diagnosing the circuit, this error signal ERR is used.
A circuit for output switching is constructed by each of the gates 15 to 18 so as to be directly visible. In other words, the test signal TE
The direct output of the parity checker 12 can be seen as the output signal Aout by ST2. Note that "person" is an output from a logic circuit (not shown).

[Problem that the invention seeks to solve]

In this way, conventionally, the test signal TB8T1-m was inputted from the outside in order to obtain the output of each part within the integrated circuit IO. In other words, it was necessary to provide a special input terminal in the circuit IO itself for inputting the test signal TB8Tl-m.

As is well known, in the L8I and the like, a large number of input/output terminals are provided for connecting address data lines, data lines, or control lines. Therefore, in reality, it is impossible to provide a special test terminal as in the method described above. Alternatively, even if a limited number of test terminals can be provided, there are many problems associated with specifying multiple types of tests for each part of the circuit. Furthermore, even if it is possible to provide a test terminal, this terminal is not used during normal operation (when installed in the device).
K is an unnecessary terminal that is not used, and there is a big problem that it is completely wasted. Furthermore, if a valid signal is erroneously applied to a test terminal that is not used during normal operation, there is a concern that the integrated circuit may undesirably enter a test mode.

[Means for solving problems]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, an object of the present invention is to provide a diagnostic method that makes it possible to specify a desired type of test mode only at the time of diagnosis without providing an input terminal for specifying a test mode. There is something to do.

To this end, in the present invention, a memory circuit such as a register that stores the test mode is provided in the integrated circuit, and data indicating the test mode is written to this memory circuit using a normal access operation from the outside. It is configured to be read (set). Furthermore, during normal operation, this memory circuit is always maintained in a reset state.

[For production]

That is, in the present invention, the test mode is handled as data supplied from the outside, and one or more address maps are assigned to the memory circuit provided in the integrated circuit. Therefore, the test mode can be set using the normal ``T access operation (access to memory, etc. by outputting address and data)''. The present invention will be explained in detail below using Examples.

〔Example〕

FIGS. 1A and 1B are diagrams showing an embodiment of the present invention, and parts common to FIGS. 2A and 2B are given the same reference numerals.

FIG. 1+al shows the configuration when a single integrated circuit IO is diagnosed by a diagnostic device. As shown in the figure, in this embodiment, a register 22 is provided which is generated inside the circuit in place of the test signal TBST which is conventionally supported from the outside via an input terminal. A specific address is assigned to this register 221C.

Therefore, an address assigned to the register 22 is issued from a diagnostic device (not shown), and data indicating the test mode is output. This address is supplied to address decoder 21. The decoder 21 issues a chip select signal that activates the register 22 indicated by the given address.
As a result, the data output from the diagnostic device is set in the register 22. As a result, each bit information rl and OJ of the data set in the register 22 is issued as a test signal TFf8Tl-m.

Although the address decoder 21 shown in the embodiment is omitted in FIG. 2, it can be considered to be an existing one provided in the integrated circuit 10. During normal operation, it is used to decode the address of a processing device such as a processor.

FIG. 1 1bl shows a configuration when this integrated circuit 10 is mounted and operated in a device or the like.

As shown in the figure, the processing of the processor 30, etc. if! The device is connected to the control line, address line, and data line.

As a result, the processor 30 presets data in a buffer or the like in the circuit lO (not shown), and
If you use the calculation and data processing functions of , it becomes k.

In this case, the address map (space) generated by the processor 30 does not include the address assigned to the register 22. However, it is possible that the register 22 may be erroneously accessed due to a runaway of the processor 30 or the like.

Therefore, in this embodiment, the reset terminal length of the register 22 is always enabled (level "O") when installed in the device.
Provide means to do so. In other words, 1. KO is always applied to the register reset terminal 23 of the integrated circuit lO corresponding to the reset terminal R.
For example, the grounding mechanism 24
It is intended to provide

As a result, the register 22 is always in a reset state, and even if the processor 30 makes an erroneous access, it is possible to prevent the test signal TENT from erroneously becoming the @l# level.

〔Effect of the invention〕

As described above, according to the present invention, a desired type of test mode can be set in an integrated circuit without providing a test terminal. Therefore, the operation of each part of the integrated circuit can be diagnosed, and the diagnostic rate can be improved. Furthermore, during normal operation, the memory circuit for setting the test mode is always in the KI7 set state, so even if the memory circuit is accessed by a processor or the like, there is no chance that undesired test mode data will be set in this memory circuit. It also disappears.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, and FIG.
1 is a diagram showing an example of connection during diagnosis; BL is a diagram showing an example of connection during normal operation. FIG. 2 is a diagram showing a conventional diagnosis method. Diagnostic method 1↑Sen Figure 1 (Q) ■Figure 14 showing J Go and Yu when using $7 + I21tb)

Claims (1)

[Claims] A system comprising an integrated circuit that includes a logic circuit group and has address and data input terminals to be accessed by a processing device, wherein the integrated circuit includes the input terminals. A memory circuit is provided in which data indicating the test mode is set through the input terminal, and during diagnosis, data indicating the test mode is set in the memory circuit from an external diagnostic device via the input terminal, and the outputs of each part of the built-in logic circuit group are output. and during normal operation accessed by said processing device:
A method for diagnosing an integrated circuit, characterized in that the memory circuit is always maintained in a reset state.