JPH06195477A - Lsi incorporating cpu - Google Patents

Abstract

PURPOSE:To make an LSI have a simple constitution where the input/output of a signal for performing the operation check between the outside of the LSI incorporating a CPU and a CPU peripheral circuit is unnecessitated and a special observation terminal for the operation check is not required. CONSTITUTION:The LSI is provided with an IN terminal register 26 for storing the test data to be imparted from a CPU for the operation test for a CPU peripheral circuit 3, an OUT terminal register 24 for storing the result of the operation test in the CPU peripheral circuit 3 based on the test data stored in the IN terminal register 26, and test switching circuits 20, 22 switching the input/output terminal of the CPU peripheral circuit 3 (OUT 1 to OUTn, IN 1 to IN n) to the connection of the IN terminal register 26 and the OUT terminal register 24 when the operation test of the CPU peripheral circuit 3 is performed. The operation test of the CPU peripheral circuit 3 is performed by performing the reading and writing for the IN terminal register 26 and the OUT terminal register 24 by the CPU.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU-embedded LSI in which a CPU (central processing unit) and peripheral circuits are formed as a single LSI.

[0002]

2. Description of the Related Art In recent years, a CPU (Central Processing Unit) and a peripheral circuit have a CPU-embedded LS configured as a single LSI.
It is said that I is configured as one LSI by adding a gate (user gate) according to the purpose of use to the CPU, which has been a separate chip up to that point, and a CPU peripheral circuit having a terminal as shown in FIG. Techniques are being adopted.

FIG. 5 shows C constructed as described above.
An example of a PU-embedded LSI is shown. As shown in FIG. 5, the CPU 1 and the user gate 2 are connected to each other, and the CPU
1 and the user gate 2 are connected to the CPU peripheral circuit 3 via the TEST switching circuits 4a and 4b. The CPU peripheral circuit 3 includes, for example, a timer, an interrupt controller, a DMAC (Direct Memory Access Controle).
r) etc., and as shown in FIG.
It exists as I.

As shown in FIG. 5, in a CPU-embedded LSI,
In order to check the operation of the CPU peripheral circuit 3, TE
ST switching circuits 4a and 4b are provided. Since the CPU peripheral circuit 3 is originally one LSI, there is a single test pattern for this circuit. Therefore, even when trying to check the built-in CPU peripheral circuit 3, the existing test pattern can be used.

However, since the terminals of the CPU peripheral circuit 3 do not match the terminals of the CPU-embedded LSI,
CPU peripheral circuit 3 directly from the terminal of the CPU embedded LSI
It is necessary to use the TEST switching circuits 4a and 4b in order to access and access the existing test pattern.

That is, the same terminal as the CPU peripheral circuit 3 is provided as a TEST observation terminal in the TEST switching circuits 4a and 4b, a test pattern is given from this TEST observation terminal, and a test result (output pattern) is outputted from a predetermined terminal. An operation test is performed by switching the input and output to and.

[0007]

As described above, the conventional CP
In the U-embedded LSI, the TEST switching circuits 4a and 4b are provided to check the operation of the CPU peripheral circuit 3, and a TEST observation terminal for directly accessing the outside of the CPU-embedded LSI is required. Also, TE
CPU-embedded LSI via the ST switching circuits 4a and 4b
An operation check was performed between the outside of the CPU and the CPU peripheral circuit 3.

Therefore, as the circuit configuration of the CPU-embedded LSI becomes complicated, the design labor is increased, and the TE
Due to the presence of the ST switching circuits 4a and 4b, there is a problem that the characteristics of the original signal are deteriorated. Furthermore, the CPU peripheral circuit 3 is provided from outside the CPU-embedded LSI.
On the other hand, it was necessary to input and output a signal for operation check.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to provide an external CPU and a C-embedded LSI.
An object of the present invention is to provide a CPU-embedded LSI having a simple configuration that does not require the input / output of signals for performing an operation check with a PU peripheral circuit and does not require a special observation terminal for operation check.

[0010]

That is, a CPU-embedded LSI according to the present invention is a CPU-embedded LSI in which a CPU and a CPU peripheral circuit are incorporated together.
A first storage unit for storing test data given from the CPU for an operation test on the U peripheral circuit, and an operation in the CPU peripheral circuit based on the test data stored in the first storage unit. A second storage unit for storing the test result and an input / output terminal of the CPU peripheral circuit when the operation test of the CPU peripheral circuit is performed, the first storage unit and the second storage unit. And a switching means for switching the connection to
It is characterized in that the operation test of the peripheral circuit is performed by the CPU reading / writing from / to the first storage means and the second storage means.

[0011]

That is, the test data is not given to the CPU peripheral circuit from the outside of the CPU peripheral circuit and the result is not directly output to the outside, but the CPU incorporated together with the CPU peripheral circuit is used to make the CPU peripheral circuit. The operation check of is executed.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

1 and 2 are block diagrams showing the circuit configuration of a CPU-embedded LSI according to the present invention. In the CPU-embedded LSI shown in FIG. 1, the CPU 10, the user gate 12, and the new CPU peripheral circuit 14 are configured as one LSI. CPU 10, user gate 1
2. The new CPU peripheral circuit 14 is connected to each other. Further, the CPU-embedded LSI shown in FIG. 2 has the same configuration as that shown in FIG.
The test memory 16 in which the program is stored is added.

New CPU peripheral circuit 14 in the present invention
Has a configuration as shown in FIG. As shown in FIG. 3, the new CPU peripheral circuit 14 of the present invention has the same CPU peripheral circuit 3, test switching circuit 20, and test switching circuit 20 as those shown in FIG.
22, OUT terminal register 24, IN terminal register 26
Is provided.

The CPU peripheral circuit 3 includes, for example, an 8-bit data terminal (D) and a read / write control terminal (Read, W).
rite), chip select terminal (CS), output terminal (OUT1
To OUTn) and input terminals (IN1 to INn) are provided. Data terminal (D), read / write control signal terminals (Read, Write), and chip select terminal (C
S) is connected to the CPU 10, the output terminal is via the test switching circuit 20, and the input terminal is the test switching circuit 2
2 are connected to the user gates 12 respectively.

The test switching circuit 20 includes output terminals (OUT1 ...
The output from OUTn) is switched to either the user gate 12 or the input end of the OUT terminal register 24. The test switching circuit 22 switches between input to the input terminals (IN1 to INn) or input from the IN terminal register 26.

In the test mode, the IN terminal register 26 latches the test pattern supplied from the CPU 10 via the data line (connected to the data terminal) in response to the write signal. OUT terminal register 24
Read (Rea) the test result (output pattern) given through the test switching circuit 20 in the test mode.
d) Output to the CPU 10 via the data line according to the signal. Next, the operation of this embodiment will be described. Here, the case of the configuration shown in FIG. 1 will be described.

The test pattern for the new CPU peripheral circuit 14 is created on the assumption that the new CPU peripheral circuit 14 is directly connected to the CPU 10. That is, the input and output of the test pattern are all I / O registers (OUT
All terminals can be accessed only by reading / writing data from / to the terminal register 24, IN terminal register 26). Therefore, it can be created in the same manner as a normal test pattern.

When checking the operation of the new CPU peripheral circuit 14, the CPU 10 operates according to the operation check program. In addition, the new CPU peripheral circuit 14 is
A signal (TEST) is applied to enter the test mode.

The CPU 10 outputs the programmed test pattern via the data line and causes the IN terminal register 26 to latch the write test signal. In the test mode, the test switching circuit 22 switches to output the signal from the IN terminal register 26 to the input terminals (IN1 to INn). As a result, the text pattern is input from the input terminals (IN1 to INn) of the CPU peripheral circuit 3,
The operation check is executed.

Check result in the CPU peripheral circuit 3,
That is, the output pattern is output from the output terminals (OUT1 to OUTn). In the test mode, the test switching circuit 20 switches to output signals from the output terminals (OUT1 to OUTn) to the OUT terminal register 24. Therefore,
The output pattern is latched in the OUT terminal register 24. The CPU 10 reads the data latched in the OUT terminal register 24 via the data line by the read signal.

In this way, the new CPU peripheral circuit 14 incorporated together with the CPU 10 is output from the CPU 10 by OUT.
The test can be performed only by reading / writing data from / to the terminal register 24 and the IN terminal register 26. Therefore, TE
A terminal for inputting / outputting signals to / from the outside such as an ST observation terminal becomes unnecessary. Therefore, the structure is simplified and the characteristics are not deteriorated.

If the new CPU peripheral circuit 14 shown in FIG. 3 is used in different types of CPU-embedded LSIs,
There is no need to create a new switching circuit for testing. Therefore, the work load for designing can be reduced.
By providing the test memory 16 as shown in FIG. 2, the self-test circuit can be easily configured.

[0024]

As described above, according to the present invention, a CPU-embedded LSI in which a CPU and a CPU peripheral circuit are incorporated together
In a first storage means for storing test data given from the CPU for an operation test on the CPU peripheral circuit, and the CPU periphery based on the test data stored in the first storage means. Second storage means for storing a result of an operation test in the circuit, and an input / output terminal of the CPU peripheral circuit when performing an operation test of the CPU peripheral circuit, the first storage means and the second storage means. Switching means for switching to the connection of the memory means of the CPU, the operation test of the CPU peripheral circuit, the CP
Since the U reads and writes to the first storage means and the second storage means, the CP and
It is possible to provide a CPU-embedded LSI having a simple configuration that does not require input / output of signals for performing an operation check with U peripheral circuits and does not require a special observation terminal for operation check.

[Brief description of drawings]

FIG. 1 is a CPU-embedded LSI according to an embodiment of the present invention.
Block diagram showing the circuit configuration of FIG.

FIG. 2 is a block diagram showing a circuit configuration of a CPU-embedded LSI provided with a test memory 16 in the configuration shown in FIG.

FIG. 3 is a block diagram showing the configuration of a new CPU peripheral circuit 14 according to the present invention.

FIG. 4 is a diagram showing an example of a CPU peripheral circuit.

FIG. 5 is a block diagram showing a configuration of a conventional CPU-embedded LSI.

[Explanation of symbols]

3 ... CPU peripheral circuit, 10 ... CPU, 12 ... User gate, 14 ... New CPU peripheral circuit, 16 ... Test memory,
20, 22 ... Test switching circuit, 24 ... OUT terminal register, 26 ... IN terminal register.

Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H01L 27/04 M 8427-4M

Claims (1)

[Claims] 1. A CPU-embedded LSI in which a CPU and a CPU peripheral circuit are incorporated together, and a first storage unit for storing test data given from the CPU for an operation test on the CPU peripheral circuit. Second storage means for storing a result of an operation test in the CPU peripheral circuit based on the test data stored in the first storage means, and C for performing an operation test of the CPU peripheral circuit
Switching means for switching the input / output terminal of the PU peripheral circuit to the connection of the first storage means and the second storage means, wherein the CPU performs an operation test of the CPU peripheral circuit by the first storage means. A CPU-embedded LSI, which is performed by reading and writing to a storage unit and the second storage unit.