JPH0632048B2 - Single-chip micro computer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a single-chip microcomputer.

[Conventional technology]

In general, a single-chip microcomputer is a CP
In addition to U, it is composed of a program memory for storing instructions, a data memory for storing operation results and constants, and peripheral circuits such as input / output ports and timers. Single-chip microcomputers have contributed to higher functionality and cost reduction of applied equipment, and have recently become more multifunctional, more input / output ports, and faster.

FIG. 2 is a block diagram showing a configuration example of an output port unit in a conventional single-chip microcomputer.
The data bus 31 is connected to the output data latch 23 that stores the data to be output, and the output of the output data latch 23 is connected to the output terminal 21 via the output buffer 22. The latch clock signal of the output data latch 23 is the output of the address decoder 29 which decodes the assigned address of the output data latch 23 and the output of the AND circuit 25 which receives the write clock signal 27 as an input. The output data latch 23 is connected to the data bus 31 via the read buffer 24, and the data stored in the output data latch 23 can be read. The read clock signal of the read buffer 24 is the output of the address decoder 29 and the output of the AND circuit 26 to which the read clock signal 28 is input. The address bus 32 is connected to the address decoder 29. The range surrounded by the dotted line 30 is the output port, and generally, a single-chip microcomputer has a large number of built-in output ports assigned to different addresses. In addition to such an output port, the single-chip micro computer is provided with storage circuits such as various writable and readable flip-flops, and has built-in peripheral circuits such as timers controlled by the outputs of these storage circuits. There is. Predetermined addresses are also assigned to these storage circuits, and data is written by instructions or the stored contents are read out to the CPU side.

The operation of the circuit shown in FIG. 2 will be described. When the CPU of this single-chip microcomputer outputs the data to the output terminal 21, the address assigned to the output terminal 21 is put on the address bus 32, so that the address decoder 29
Output becomes active and the output of the AND circuit 25 becomes active in synchronization with the write clock signal 27, so that the data of the data bus 31 is latched in the output data latch 23 and latched in the output data latch 23 via the output buffer 22. The output data is output to the output terminal 21. In addition, since the stored data is used for calculation and the like, when the CPU reads the data latched in the output data latch 23, the address assigned to the output terminal 21 is put on the address bus 32 to output the output of the address decoder 29. Becomes active,
Since the output of the AND circuit 26 becomes active in synchronization with the read clock signal 28, the data latched in the output data latch 23 is transferred to the data bus via the read buffer 24.
It is output to 31.

[Problems to be solved by the invention]

In the conventional single-chip microcomputer described above, each of the memory circuits built in the peripheral circuits has a read buffer for outputting the stored data to the data bus, and the operation speed of the single-chip microcomputer is usually Since the load capacity of the data bus built in the single-chip microcomputer is affected, when the peripheral circuit increases, the number of read buffers connected to the data bus increases and the output load capacity of the read buffer causes There is a drawback that the load capacity of the data bus increases and the operating speed decreases,
In addition, increasing the load drive capacity of the read buffer to increase the operation speed also increases the read buffer output load capacity by increasing the on-chip area of the read buffer, thus increasing the number of read buffers. When it is connected to the data bus, the output load capacity of another read buffer becomes a part of the load capacity of the data bus when viewed from one read buffer, which is not very effective in increasing the operation speed. It has the drawback of not going up.

[Means for solving problems]

The single-chip microcomputer of the present invention is the first
Storage means, second storage means electrically connected to the output terminal, and data to be written in response to a data write request to the second storage means together with the second storage means. Means for writing to a corresponding address of the memory means, and the first memory instead of the second memory means in response to a data read request from the second memory means.
Means for accessing the storage means and reading the data from the corresponding address of the first storage means.

[Action]

Therefore, it is possible to reduce the number of read buffers connected to the data bus, reduce the load capacity of the data bus,
It becomes possible to increase the operation speed of the single-chip micro computer.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a part of an embodiment of a single chip microcomputer of the present invention.

A memory cell array 7, which is a first memory circuit that can be written and read by an instruction of a single-chip micro computer, is provided through a write buffer 11 and a read buffer 12.
Is connected to the data bus 13 via. The address decoder 8 outputs a selection signal group 17 for selecting all the bits in the memory cell array 7, and the selection signal group 17 is an OR circuit 18
To enter. The write clock signal of the write buffer 11 is the output of the AND circuit 15 that receives the write clock signal 6 and the output of the OR circuit 18, and the read clock signal of the read buffer 12 is the output of the read clock signal 10 and the output of the OR circuit 18. It is the output of the AND circuit 16 that receives the input. The input of the output data latch 3, which is a second memory circuit writable by an instruction, is connected to the data bus 13, and the output is connected to the output terminal 1 via the output buffer 2. The latch clock signal of the output data latch 3 is the output of the AND circuit 4 which receives the write clock signal 6 and the output of the address decoder 5. The inputs of the address decoder 5 and the address decoder 8 are connected to the address bus 14.
The range of the dotted line 15 is one output port, and this single-chip microcomputer also has many built-in peripheral circuits such as output ports assigned to different addresses. Take as an example.

Next, the circuit operation of this embodiment will be described.

(1) CPU of this single-chip microcomputer
Outputs data to output terminal 1. In this case, by putting the address assigned to the output terminal 1 on the address bus 14, the output of the address decoder 5 becomes active. Therefore, since the output of the AND circuit 4 becomes active in synchronization with the write clock signal 6, the data bus 13
Is stored in the output data latch 3, and is output to the output terminal 1 via the data output buffer 2 stored in the output data latch 3. Further, since the address space assigned to the memory cell array 7 includes the address assigned to the output terminal 1, when the address assigned to the output terminal 1 rides on the address bus 14, the address decoder 8 decodes the address bus 14. Then, the signal of the same address as the output terminal 1 in the selection signal group 17 is activated. Therefore, the bit of the same address as the output terminal 1 in the memory cell array 7 is selected, and the output of the OR circuit 18 becomes active, so that the output of the AND circuit 15 becomes active in synchronization with the write clock signal 6 and the data is output. Data on the bus 13 is transferred via the write buffer 11 to the memory cell array 7
Is written to the bit of the same address as the output terminal 1 of the. That is, when the CPU outputs data to the output terminal 1, the data is output to the output data latch 3 and the memory cell array 7.
Will be written to both the output terminal 1 and the bit assigned to the same address.

(2) CPU of this single-chip micro computer
When reading the contents of output data latch 3. in this case,
By putting the address assigned to the output terminal 1 on the address bus 14, the address decoder 8
14 is decoded, and the signal of the same address as the output terminal 1 in the selection signal group 17 is activated. Therefore, the bit of the same address as the output terminal 1 in the memory cell array 7 is selected, and the output of the OR circuit 18 becomes active, so that the output of the AND circuit 16 becomes active in synchronization with the read clock signal 10 and the memory The data stored in the bit of the same address as the output terminal 1 in the cell array 7 is output to the data bus 13 via the read buffer 12.
When the address assigned to the output terminal 1 is placed on the address bus 14, the output of the address decoder 5 becomes active, but the output data latch 3 stores it because there is no circuit for reading the data stored in the output data latch 3. The generated data is not output to the data bus 13. That is, C
When the PU reads the contents of the output data latch 3, it must read the contents stored in the bit of the same address as the output terminal 1 in the memory cell array 7 in which the same contents as the output data latch 3 are stored. become.

In general, a single-chip microcomputer is a data memory that has a built-in memory (dynamic random access memory, static random access memory, etc.) cell array that considers the circuit configuration so that the area on the chip is smaller than that of a normal logic element. In many cases, if the memory cell array 7 of FIG. 2 is added to a data memory that stores constants and the like and an address decoder of the data memory (address decoder 8 of the memory cell array 7) is added, it is possible to write to the memory cell array.
It can also be used as the data memory of the circuit necessary for reading, and the chip area can be reduced. Further, the write information of the output data latch 3 may be output to the logic circuit.

〔The invention's effect〕

As described above, according to the present invention, in a single-chip microcomputer, a predetermined address is assigned, the first storage means capable of writing data and reading the stored data by a command of the CPU, and the first storage means. The second memory means is assigned the same address as the means, is writable only by a command from the CPU, and outputs the write information to a predetermined logic circuit, and the CPU of the single-chip microcomputer writes data to the logic circuit. When writing, write to both the second storage means and the first storage means, and when reading data written in the logic circuit, write to the second storage means.
By reading from the first storage means rather than from the first storage means, the number of read buffers connected to the data bus is reduced, the load capacity of the data bus is reduced, and the operation of the single-chip microcomputer is reduced. It has the effect of increasing the speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a part of an embodiment of a single-chip micro computer of the present invention, and FIG. 2 is a block diagram of a configuration example of an output port section in a conventional single-chip micro computer. 1 ... Output terminal, 2 ... Output buffer, 3 ... Output data latch, 4, 15, 16 ... AND circuit, 6 ... Write clock signal, 5, 8 ... Address decoder, 7 ... Memory cell array, 17 ... Selection signal group for selecting the memory cell array 7, 18 ... OR circuit, 10 ... Read clock signal, 11 ... Write buffer, 12 ... Read buffer, 13 ... Data bus, 14 ... Address bus, 15 …… Output port.

Claims (1)

[Claims] 1. A first storage means, a second storage means electrically connected to an output terminal, and data to be written in response to a data write request to the second storage means. A means for writing to a corresponding address of the first storage means together with the storage means, and a means for accessing the first storage means instead of the second storage means in response to a data read request from the second storage means. And a means for reading data from the corresponding address of the first storage means.