JPH02168362A - Semiconductor storage circuit - Google Patents

Abstract

PURPOSE:To make a chip surface small by providing a peripheral storage circuit and a random access memory (RAM) to commonly hold the data of the contents equal to the peripheral storage circuit. CONSTITUTION:At the time of writing data to a peripheral latch 2, the data are simultaneously written to a RAM 1 having the same address, and at the time of reading the data, the data from the RAM 1 are read. At such a time, for the number of transistors, though a several number in decode parts is increased, since the size of an output buffer transistor is sufficiently larger than it and a capacity load to a bus line is made small, the size of an output buffer 3 from the RAM 1 is also made small. Thus, the chip size can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor memory circuits, and more particularly to peripheral memory circuits for bus-type microcombination devices.

[Conventional technology]

Conventionally, this type of semiconductor memory circuit has a buffer transistor in the output buffer 12 of the peripheral buffer for each peripheral latch 2 to carry a signal from the bus 61.

Here, a bus driver 3 and an input buffer 74 are interposed between the RAM (random access memory) l and the internal bus 6, and an input buffer 75 and an input buffer 74 are interposed between the peripheral latch 2 and the internal bus 6. An output buffer 12 is interposed, and the data read signal 7 and the address signal are manually ANDed.
Apply the circuit output to the input capacitor 7a5I and send the address signal 8
The output of a two-man-operated AND circuit of and the write signal 9 is applied to the output buffer 12.

[Problem to be solved by the invention]

In the conventional semiconductor memory circuit described above, each latch 2 has an output buffer 7 transistor in the output buffer 12. The transistor of Jin's output buffer 12 is
Since they are larger than normal logic gates, they have the disadvantage of increasing the area of the semiconductor chip.

Furthermore, as the number of peripheral memory circuits increases, the capacitive load on the bus 6I becomes larger (which in turn increases the size of the bus 6I, including other bus drivers 3).

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory circuit which solves the above-mentioned drawbacks and allows the bus driver to be omitted and the semiconductor chip area to be reduced.

[Means to solve the problem]

The structure of the semiconductor memory circuit of the present invention is characterized by comprising a peripheral memory circuit of a pass-type microcomputer and a random access memory that commonly holds data of the same content as the peripheral memory circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor memory circuit according to an embodiment of the present invention. In FIG. 1, the semiconductor memory circuit of this embodiment includes a RAM 1, a peripheral latch 2, and an internal bus 6 (!: R
A bus driver 3 for inputting and outputting data to/from AM1, an input buffer 4, an input buffer 5 for inputting and outputting data between the internal path 6 and the peripheral latch 2, a read signal 7, and an address signal. 802 human-powered first AND circuit, and two-human powered second AND circuit of address signal 8 and write signal 9.
and an AND circuit. Here, the first A
The output of the ND circuit is applied to the path driver 3, and the output of the second AND circuit is applied to the input buffer 4.5.

That is, the semiconductor memory circuit of this embodiment does not have a bus driver for outputting signals to path 6.

Now, when data is written to the peripheral latch 2, data is simultaneously written to RAM1 having the same address, and when data is read, data is read from RAM1.

Comparing this circuit with the conventional circuit (Fig. 3), it is found that the RAMI
The number of cell units and address decoding units has been increased, and the number of output buffers 12 and write signal decoding units has been decreased.

At this time, although the number of transistors increases by several in the decoding section, the size of the output buffer transistor is sufficiently larger than that, and the capacitive load on the pass line is smaller in the circuit of this embodiment.
The size of the output buffer 3 from I is also smaller compared to the conventional number of times.

Therefore, the circuit of this embodiment can have a smaller chip size than the conventional circuit.

FIG. 2 is a block diagram of a semiconductor memory circuit according to another embodiment of the present invention. In FIG. 2, the circuit of this embodiment has the first
A new selector 10 has been added to select whether or not to write the same data as RAM 1 to latch 2 at the periphery of the figure, and this allows the RAM area to be used differently for holding data in normal RAM and peripheral latches. , the RAM area can be used effectively.

〔Effect of the invention〕

As explained above, the present invention achieves
This has the effect of reducing chip size.

FIG. 3 is a block diagram of a conventional semiconductor memory circuit.

l...RAM, 2...Peripheral latch, 3
...RAM bus driver, 4...R
Input buffer to AM, 5... Input buffer of peripheral latch, 6... Internal bus, 7...
Data read signal, 8... Address number,
9...Write signal, lO...Selector for writing to peripheral latch, 11...Write signal to peripheral latch, 12...Output of peripheral buffer buffer.

Agent: Susumu Uchihara, Patent Attorney 4, Drawing 1 Brief Explanation Fig. 1 is a block diagram of a semiconductor memory circuit according to one embodiment of the present invention, and Fig. 2 is a block diagram of a semiconductor memory circuit according to another embodiment of the present invention.

Claims (1)

[Claims] 1. A semiconductor memory circuit comprising a peripheral memory circuit of a bus type microcomputer and a random access memory that holds data in common that is the same as that of the peripheral memory circuit.