JPH0660661A - Semiconductor integrated device - Google Patents

Abstract

PURPOSE:To curtail an access time to the time only for the read operation by connecting, when the read and write operations occur simultaneously, a write bit line and a read bit line and disconencting a memory cell and the read bit line. CONSTITUTION:During the read/write operations, a read word line WLR, a write word line WLW and a column write enable CWE and at the high level. In this case, since transfer gates W, E are in the ON condition, a signal of the write bit line BLW is outputted to a memory cell node m to write a signal to the memory cell. Meanwhile, since the transfer gates a, b, c, d, R turn on, while the transfer gate e turns off, a signal of the bit line BLW is outputted to the read bit line BLR. When the word lines WLR, WLW are at the high level and the enable CWE is at the low level, the gates a, b, d, e, R turn on, the gate c turn off and an access time is defined by the switching time of the gate c and can be equalized to the time in the read operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated device, and more particularly to improvement of a multiport RAM.

[0002]

2. Description of the Related Art Conventionally, a multi-port RAM is known as a RAM that can read and write from a plurality of independent ports. FIG. 3 shows the conventional multi-port RA.
In the circuit diagram showing M, 1 and 2 are inverters that form a flip-flop. A logic 0 or a logic 1 is stored using this flip-flop as a memory cell. 3 is a buffer gate, and R, W and E are transfer gates.

When reading the stored contents of a memory cell,
As shown in FIG. 4A, the read word line WLR is set to the high level and the transfer gate R is turned on. As a result, the stored content of the memory cell is output to the read bit line BLR via the buffer gate 3 and the transfer gate R, and the stored content is read. FIG. 4E shows a signal read to the read bit line BLR.

On the other hand, when writing information to the memory cell, the write word line WLW is set to the high level as shown in FIG. 4B, and the column write enable CWE is set to the high level as shown in FIG. 4C. Become. This allows
The transfer gates W and E are turned on, and the write BLW and the node m of the memory cell are connected to each other, whereby the signal of the write bit line BLW is written in the memory cell. FIG. 4D shows a write signal of the write bit line BLW. Here, in order to prevent the information from being written to other than the selected memory cell, the column write enable CWE is set to the high level after the write word line WLW is set to the high level as shown in FIGS. 4B and 4C. The write setup time t _SA is set by the time.

[0005]

However, the conventional multi-port RAM has the following problems when reading and writing occur simultaneously. That is, the access time at the time of reading is determined by the switching time of the transfer gate R, but when the reading and the writing occur at the same time, the access time t _AA is as shown in FIG.
As shown in, the addition value of t _SA and t _AW is obtained. As described above, t _SA is the setup time and t _AW is the write access time, which is the time from when the column write enable CWE becomes high level until the signal on the write bit line BLW appears on the read bit line BLR. The write access time t _AW is the sum of the switching time of the transfer gate E, the delay time of the inverter 1 and the delay time of the buffer gate 3. As described above, in the conventional case, there is a problem that the access time is significantly increased when reading and writing occur at the same time as compared with reading only.

The present invention has been made in order to solve such a problem, and it is possible to effectively prevent an increase in access time and perform high-speed access even when reading and writing occur simultaneously. It is an object of the present invention to provide a semiconductor integrated device as described above.

[0007]

In a multi-port RAM in which a read word line and a write word line are separated, a semiconductor integrated device of the present invention outputs a write signal to a read bit line when read and write occur simultaneously. It is realized by providing a transfer gate for connecting to the memory cell and a transfer gate for disconnecting the memory cell and the read bit line.

Also, in the semiconductor integrated device of the present invention, in a multi-port RAM in which a read word line and a write word line are shared, when a read and a write occur simultaneously, a write signal is connected to the read bit line. And a transfer gate for disconnecting the read bit line from the memory cell.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the semiconductor integrated device of the present invention. In FIG. 1, the same parts as those of the conventional device shown in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted in this embodiment. In FIG. 1, a, b,
c is a write bit line BLW and a read bit line BLR
Is a transfer gate connected in cascade between the two. These transfer gates a, b and c are N-type MOS transistors. The gate electrode of the transfer gate a is connected to the write word line WLW, the gate electrode of the transfer gate b is connected to the read word line WLR,
The gate electrode of the transfer gate c is connected to the column write enable CWE via the transfer gate d. The gate electrode of the transfer gate d is connected to the write word line WLW. Further, a transfer gate e of a P-type MOS transistor is connected between the output of the buffer gate 3 of the memory cell and the transfer gate R. The gate electrode of the transfer gate e is connected to the column write enable CWE via the transfer gate d.

Next, the operation of this embodiment will be described.
First, in the non-selected state, both the write word line WLW and the read word line WLR are at low level, the column write enable CWE is Don't Care, and the transfer gates R, a, and b are off. Therefore, at this time, the information of the memory cell is read out from the read bit line BL regardless of the column write enable CWE.
Not output to R.

In the case of reading / non-writing, the read word line WLR is at high level and the write word line WL is
W is low level, column write enable CWE is Do
It isn't Care. Therefore, since the transfer gate d is turned off and the transfer gates e and R are turned on, the stored contents of the memory cell are output to the read bit line BLW regardless of the column write enable CWE.

In the case of non-read / write, the read word line WLR is at low level and the write word line WLW.
Is at a high level, and the column write enable CWE is at a high level. In this case, since the transfer gates W and E are turned on, the signal of the write bit line BLW is output to the node m of the memory cell, and the signal is written in the memory cell. On the other hand, since the transfer gates b and R are off, the signal of the write bit line BLW and the information of the memory cell are not output to the read bit line BLR.

In the case of reading / writing, the read word line WLR, the write word line WLW, and the column write enable CWE are all at high level. in this case,
Since the transfer gates W and E are on, the signal of the write bit line BLW is written in the memory cell as described above. On the other hand, transfer gates a, b, c,
Since d and R are on and transfer gate e is off,
The signal of the write bit line BLW is output to the read bit line BLR.

Here, the access time in the case of read / write is the delay time from the time when the column write enable CWE becomes high level until the signal of the write bit line BLW appears on the read bit line BLR (t _AW described above). Is determined by. Conventionally, this delay time is the total value of the switching time of the transfer gate E and the delay times of the inverter 1 and the buffer gate 3, as described in FIG.

On the other hand, in this embodiment, when the read word line WLR and the write word line WLW are at the high level and the column write enable CWE is at the low level, the transfer gates a, b, d, e and R are on and the transfer gates are on. Since the gate c is off, the access time is only the switching time of the transfer gate c. Therefore, the gate speed can be increased by two stages as compared with the related art, and the access time can be made almost equal to that at the time of reading even when reading and writing occur simultaneously.

FIG. 2 is a circuit diagram showing another embodiment of the present invention. This embodiment is an example of a multiport RAM in which a read word line and a write word line are commonly used. In the figure, WLRW is the common read / write word line. Further, here, the transfer gate b shown in the embodiment of FIG. 1 is deleted. The operation is as described in the embodiment of FIG. 1, but there is no read / non-write or non-read / write operation. Also,
Switching between read and write operations is performed by switching the column write enable CWE between high level and low level. Even in this embodiment, when reading and writing occur at the same time, the access time is determined by the switching time of the transfer gate c, so that the access time is the same as that for reading only.

[0017]

As described above, according to the present invention, when reading and writing occur simultaneously, by connecting the write bit line and the read bit line and disconnecting the memory cell and the read bit line, the access time is reduced. There is an effect that can be shortened to the same level as when only reading.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor integrated device of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional multiport RAM.

FIG. 4 is a time chart showing the operation of a conventional multiport RAM.

[Explanation of symbols]

 1, 2 inverters 3 buffer gates R, W, E transfer gates a to e transfer gates m memory cell nodes

Claims (2)

[Claims] 1. In a multi-port RAM in which a read word line and a write word line are separated, a transfer gate for connecting a write signal to a read bit line and a read operation when a read and a write occur simultaneously. A semiconductor integrated device comprising a transfer gate for disconnecting a bit line. 2. A transfer gate and a memory cell for connecting a write signal to a read bit line when reading and writing occur simultaneously in a multi-port RAM in which a read word line and a write word line are shared. A semiconductor integrated device comprising a transfer gate for disconnecting a read bit line.