JPS63255896A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To decrease a layout area by providing a control circuit to generate an activating signal, a word line pulse generating circuit controlled by the activating signal and a data latch circuit connected by every digit line. CONSTITUTION:A word line pulse generating circuit E1 is controlled by an activating signal phi generated from a control circuit CON, generates the pulse of an (1/2) Vcc level at a word line WL1 for a constant time only at the time of reading and generates the pulse of the Vcc level at the word line WL1 for the constant time only at the time of writing. Data latch circuits C1 and C2, at the time of the reading, latch and amplify the data from a memory cell to appear on the selected digit line, at the time of writing, latch the data from a writing circuit DIB to appear on the selected digit line and write them to the selected memory cell. Thus, since the area of the memory cell can be minimized, the chip area of the LSI memory can be minimized.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor memory device composed of a MOSFET (insulated gate field effect transistor), and a semiconductor memory device that is effective for a static RAM (random access memory). Regarding storage devices.

[Conventional technology]

Conventionally, semiconductor memory bags W (hereinafter abbreviated as LSI memory) are
The configuration is as shown in FIG.

In FIG. 3, terminals Ax-Ay-Din-D.

ut-WE and UT-WE are its external terminals. Note that the power supply terminal is omitted in FIG. 4. A specific circuit for one of the memory cells MC1 to MC4 is shown. The X address decoder X-DCR is composed of logic gate circuits G1/02 and the like. As inputs to these logic gate circuits G1, G02, etc., an external address signal Ax supplied from an appropriate circuit device (not shown) is received by an X address buffer X-ADB. The internal complementary address signals axO to axi processed here are applied in a predetermined combination. Word line WLI is selected by X-address decoder X-DCR, and word line WL1 when selected is raised to VCC level.

The same applies to the other word line WL2.

MOSFETQ5 and Q6 that make up the column switch circuit
A selection signal is supplied from the Y address decoder Y-DCR to the gates of Q7 and Q8, respectively. This Y address decoder Y-DCR is a logic gate circuit G3/G
Consists of 4th grade. These logic gate circuits G3・
04, etc., an external address signal Ay supplied from an appropriate circuit device (not shown) is received by the Y address buffer Y-ADB. The internal complementary address signals ayo-ayi processed here are applied in a predetermined combination.

A pair of digit lines DO, Do and Dl in the array of memory cells MC1 to MC4 are transmission gate MOSFETs C5 for digit line selection, respectively.
- Connected to common data lines CD and σ through a column switch circuit composed of C6, C7, and C8.

This common data line CD-CD has a readout circuit D.
The input terminal of OB and the output terminal of write circuit DIB are connected. The output terminal of the read circuit DOB sends a read signal to the data output terminal Dout, and the input terminal of the write circuit DIB is applied with a write data signal supplied from the data input terminal Din. The readout circuit DOB includes a sense amplifier and has a data output terminal Do.
A read signal is sent from ut.

[Problem that the invention seeks to solve]

However, conventional semiconductor memory devices have the disadvantage that the layout area increases as the degree of integration of LSI memory increases in recent years, the number of bits increases, and the cell array occupies most of the chip area of the LSI memory.

An object of the present invention is to provide a control circuit that generates an activation signal in response to input of a write signal, and a word line controlled by the activation signal, in order to solve the above-mentioned drawbacks of the conventional static RAM configuration described above. An object of the present invention is to provide a semiconductor memory device having an original content including a pulse generation circuit and a data latch circuit connected to each digit line.

[Means for solving problems]

In the semiconductor memory device of the present invention, each digit line is connected to a control circuit that generates an activation signal, and a word line pulse generation circuit that is controlled by the activation signal and outputs different levels during reading and writing. and a data latch circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing the structure of an embodiment of a semiconductor memory device using a static RAM according to the present invention. This configuration differs from the conventional example shown in FIG. Pulse generation circuit E1/E2...
・It has data latch circuits C1, C2, . . . connected to each digit line.

In FIG. 1, terminals Ax-Dy-Din-Dout-
WE and CS are external terminals. Note that in FIG. 1, the power supply terminal is omitted.

One specific circuit of memory cells MC11 to MC14 is shown, and includes a drive MO8FET Qll/C12 whose gate and drain are cross-connected to each other, and a MOS
Drain of FET Qll・C12 and power supply voltage VCC
and high-resistance R11 and R12 formed of an information-retaining polysilicon layer provided between the two. Then, a transfer gate MO8 is connected between the common connection point of MOSFET Qll/C12 and high resistance R11/R12 and the complementary digit line DO/T.
FETs C13 and C14 are arranged.

Further, these memory cells MC11 to MC14 are arranged in a matrix. Same word line WLi (WLI・W
Memory cells MC11, 12, arranged in L2...)
MO6FET C13 for transfer gate of...
Gates such as C14 are connected to the corresponding word line WLI.
or commonly connected to WL2 and the same digit line Di
(DI・D2...) and D i (DI - D2
The input/output terminals of the memory cells MC arranged in .

In FIG. 1, the control circuit CON has an external terminal T
・Receives an input signal from Uy and forms an internal control timing signal.In other words, the control circuit CON receives a write enable signal from external terminal T and a chip selection signal from external terminal σW, and generates an internal control timing signal. The activation signal φ is controlled by the input signal from the external terminal T through the control circuit CON. Ru.

In FIG. 1, the X address decoder X-DCR is composed of logic gate circuits G1.02 and the like. The inputs of these logic gate circuits G1, G02, etc. are supplied with internal complementary address signals ax(, -axi) processed by an X address buffer X-ADB that receives an external address signal Ax supplied from an appropriate circuit device (not shown). , are applied in a predetermined combination.

In FIG. 1, word line WLI is selected by word line pulse generation circuit E1 which receives selection signals formed by X address decoders X and -DCR. Here, the word line pulse generation circuit E1 is connected to the control circuit CON
During reading, a pulse at the (1/2) Vcc level is generated on word line WL1 for a certain period of time, and during writing, it is controlled by activation signal φ generated from word line WL1.
A VCC level pulse is generated on LI for a certain period of time.

The same applies to the other word line WL2.

In FIG. 1, a pair of digit lines Do-Do and Dl in the memory cell array are MO9FETs for transmission gates for digit line selection, respectively.
It is connected to the common data line CD-CD via a column switch circuit composed of C5 and C6 and C7 and C8. The input terminal of the read circuit DOB and the output terminal of the write circuit DIB are connected to this common data line CD-CD. The output terminal of the read circuit DOB sends a read signal to the data output terminal Dout, and the input terminal of the write circuit DIB is applied with a write data signal supplied from the data input terminal Din. The readout circuit DOB includes a sense amplifier and sends out a readout signal from the data output terminal Dout.

In Figure 1, the MOS that constitutes the column switch circuit
A selection signal is supplied to the gates of FETs C5, C6 and C7, C8 from a Y address decoder Y-DCR, respectively. This Y address decoder Y-DCR is composed of logic gate circuits G3.04 and the like. The inputs of these logic gate circuits G3, G4, etc. are supplied with internal complementary address signals a310 to ayi processed by a Y address buffer Y-ADB that receives an external address signal Ay supplied from an appropriate circuit device (not shown). is applied by a combination of

In addition, a pair of digit lines Do-Do and Dl/DI
The data latch circuits C1 and C2 connected to
At the time of reading, the data from the memory cell appearing on the selected digit line is latched and amplified, and at the time of writing, the data from the write circuit DIB appearing on the selected digit line is latched and the data from the memory cell appearing on the selected digit line is latched and amplified. Further, data latch circuits C1 and C2, which perform writing to cells, latch data from memory cells MC appearing on digit lines other than the selected digit line.

Further, although not limited to the above operation, a resistive load is provided between each digit line and the power supply voltage VCC to protect the circuit.

Next, the operation at the time of reading will be explained with reference to the waveform diagram in FIG. Word line pulse generation circuit E1 is selected by external address signal Ax in FIG. Here, the word line pulse generation circuit E1 generates an activation signal φ(
low level), and the word line WL1 is controlled according to (1 low level).
/2) Generate a Vcc level pulse for a certain period of time. Here, the reason why a VCC level pulse is not generated on the word line WLI is because the MO3FET of the memory cell
This is because the gate width ratios between Qll and C13 and between C12 and C14, that is, Wll/W13 and W12/W14, are smaller than before, so that the data held in the memory cells is not destroyed. Also, on the word line WLI (
1/2) Since the Vcc level pulse is generated only for a certain period of time, a slight potential difference appears on the digit line only for a certain period of time. However, the data latch circuit C1 detects, latches, amplifies, and transmits the slight potential difference for a certain period of time to the output circuit DOB, so the access speed does not slow down. The same is true.

Next, the operation during writing will be explained with reference to the waveform diagram in FIG. Word line pulse generation circuit E1 is selected by external address signal Ax in FIG. here,
The word line pulse generation circuit E1 is controlled according to the activation signal φ (high level, level) generated via the control circuit CON by input signals (low level) from seven external terminals as shown in FIG. Vo on WLI. Generates a pulse for a certain amount of time at the level. Here, the level of the pulse generated on the word line WLI is set to (1/2) VCC.
The reason why this is not done is because if the level of the pulse generated on the word line WLI is set to the (1/2) Vcc level, the write time will become longer and there is a possibility that it will not be possible to write while the word line WLI is in the high state. be.

Now, the word line WLI in FIG. 1 is selected, and the word line WLI in FIG.
A constant time pulse of VCC level is generated on LI, digit line DO/Do is selected, and word line WLI and digit line are connected.

- Consider the case where writing is performed to the memory cell MC11 located at the intersection of the T-trees. Here, memory cell MCII
Data from the write circuit DIB appears on the digit lines Do to Do which are selected in order of writing. The data appearing on the digit lines DO and Y is written into the memory cell MCII, and at the same time, the data is also latched into the data latch circuit C1. That is, data is written into the memory cell MCII at high speed by the write circuit DIR1 and the data latch circuit C1.

By the way, at the time of writing, since a pulse of VCC level for a certain period of time is generated on the word line WLI, there is a possibility that the data in the memory cell MCI2 to which writing is not actually performed may be destroyed. Therefore, the word line WLI rises to the ■cc level, that is, (1/2) Vc
The data in the memory cell MC12 is latched at the data latch circuit C2 at the c level, and while the word line WLI is in the high state, the latched data is written from the data latch circuit C2 to the memory cell MC12 at any time.
Even if a VCC level pulse occurs on I, memory cell M
It is possible to avoid destroying the C12 data.

〔Effect of the invention〕

As explained above, the present invention can reduce the area of the memory cell by making the ratio of the gate width of the MO3FET for the transfer gate of the memory cell and the gate width of the MO3FET for driving the memory cell smaller than before. As a result, the area of the memory cell array, which occupies most of the chip area of LSI memory, can be reduced to 1/2 to 1/3 of the conventional area, resulting in LSI
This has the effect that the chip area of the SI memory can be reduced by 20 to 30%.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a semiconductor memory device using a static RAM of the present invention, FIG. 2 is a diagram showing the operation timing of the embodiment of the present invention shown in FIG. 1, and FIG. 1 is a configuration diagram of an example of a semiconductor memory device using a static RAM according to the prior art. CON...Control circuit, El/E2...Word line pulse generation circuit, C1/C2...Data latch circuit, X-ADB...X address buffer, Y-ADB
...Y address buffer, X-DCR...X address decoder, Y-DCR...Y address decoder, M
C11-14...Memory cell, DIB...Write circuit, DOB...Read circuit.

Claims (1)

[Claims] A semiconductor memory device includes a control circuit that generates an activation signal, a word line pulse generation circuit that is controlled by the activation signal and outputs different levels during reading and writing, and a data latch connected to each digit line. A semiconductor memory device comprising a circuit.