JPH0449196B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a random access memory constructed of a monolithic semiconductor integrated circuit, such as a static RAM (random access memory).

For example, static RAM composed of MOSFETs (insulated gate field effect transistors)
In this case, the time required for a write operation is significantly shorter than the time required for a read operation. That is, during writing, a write amplifier that receives write data of a large signal level writes to a memory cell.

On the other hand, at the time of reading, the minute signal of the memory cell must be amplified.

Since the operation cycle of the memory is defined by the slower read operation, there is a time margin during the write operation. The inventor of the present application focused on this point and considered reducing the number of external terminals.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a random access memory with a reduced number of external terminals.

Other objects of the invention will become apparent from the following description and drawings.

FIG. 1 shows a circuit of a MOS static RAM according to an embodiment of the present invention.

The RAM shown in the figure is formed on one semiconductor substrate using known semiconductor integrated circuit technology.
Terminals AX ₁ to AX _K , AY ₁ to AY, D _OUT ,
CS, /D _io , V _DD and GND are its external terminals. The illustrated RAM is operated by supplying a power supply voltage from an external power supply device 8 between its power supply terminal V _DD and the ground terminal GND.

In the figure, 1 is a memory array, which is composed of memory cells 1a to 1d, word lines _W1 to _Wn , and data lines _{Dp , p} to D0, _o . Although the memory cell is not particularly limited, 1a
Driven as shown in detail as a representative
A static flip-flop circuit consisting of MOSFETs _{Q 1} and Q ₂ and high load resistances R ₁ and R ₂ ,
The static flip-flop circuit is composed of transmission gate MOSFETs Q ₃ and Q ₄ provided between the input/output terminal and a pair of data lines D ₁ and ₁ , respectively. The above memory cell has resistors R ₁ and R ₂
The data is held by supplying the power supply voltage supplied to the power supply terminal V _DD to the connection point.

The resistors R ₁ and R ₂ are made to have a high resistance value, for example, several megohms to several gigaohms, in order to reduce the power consumption of the memory cell in the data retention state. The above resistors R ₁ and R ₂ are for example MOSFETs in order to reduce the area occupied by the memory cell.
It is composed of a relatively high resistivity polysilicon layer formed on the surface of a semiconductor substrate forming a semiconductor substrate with a relatively thick field insulating film interposed therebetween.

The memory cells 1a to 1d are arranged in a matrix as shown. That is, memory cells 1a, 1c and 1b arranged in the same row,
Transmission gate MOSFET as selection terminal such as 1d
The gates of are connected to word lines W ₁ and W _n . A pair of input/output terminals of memory cells 1a, 1b and 1c, 1d arranged in the same column are respectively connected to a pair of data lines D ₁ , ₁ and D _o , _o .

The data lines corresponding to each column are transmission gates as column switches.
It is connected to the common data line CD through MOSFETs Q ₉ , Q ₁₀ and Q ₁₁ , Q ₁₂ .

The word lines W ₁ to W _n are connected to the output terminals of the X address decoder circuit 2 and selected by the X address decoder circuit 2 .

On the other hand, MOSFETQ ₉ as a column switch,
The gates of Q ₁₀ , Q ₁₁ , and Q ₁₂ are each connected to the output terminal of the Y address decoder circuit 3 and selected by the Y address decoder circuit 3.

The X address decoder circuit 2 is supplied with address signals supplied to address input terminals AX ₁ to AX _k via address buffer circuits BX ₁ to BX _k .

The Y address decoder circuit 3 is similarly supplied with address signals supplied to address input terminals AY ₁ to AY via address buffer circuits BY ₁ to BY.

The pair of common data lines CD are connected on one side to a pair of input terminals of the sense amplifier 4, and on the other side to the output terminal of the write circuit 6 via transmission gate MOSFETs _Q13 and _Q14 .

The output signal of the sense amplifier 4 is transmitted to the input terminal of the output buffer circuit 5.

The sense amplifier 4 responds to the control circuit 7 when the chip selection signal supplied to the chip selection terminal is set to a low level such as the ground potential of the circuit.
It is activated by setting the signal CS supplied from the circuit to a high level.

The output buffer circuit 5 is substantially comprised of a three-state circuit including an output terminal flowing state. When the signal CS output from the control circuit 7 is at a low level, the output terminal D _OUT of the output buffer circuit 5 is placed in a floating state.

When the signal CS is at a high level, the output terminal _DOUT of the output buffer circuit 5 is set to a low level or a high level corresponding to the output level from the sense amplifier 4.

In this embodiment, in order to reduce the number of external terminals, the read/write signal and the input data signal are multiplexed in time series and supplied by the external terminal WE / _Dio . Although not particularly limited, the chip selection signal is used to reproduce the read/write signal WE' and the input data signal D _io ' supplied to the write circuit 6, as will be described later.

An example circuit for regenerating this multiplexed signal is shown in FIG.

The signal supplied from the external terminal/D _io above is
On the one hand, through the transmission gate MOSFETQ ₁₅ ,
The signal is taken into the input terminal of the latch circuit F/F, and on the other hand, it is supplied as is to the write circuit of FIG. 1 as an input data signal _Dio . Above transmission gate
A chip selection signal supplied from an external terminal is applied to the gate of MOSFETQ ₁₅ , and the chip selection signal is applied to the gate of MOSFETQ 15 in synchronization with the fall of the low level of this signal.
MOSFETQ ₁₅ is turned off and sampling is performed. In addition, the latch circuit F/F
Activated by CS, in synchronization with the rise of the high level of this signal CS, an inverted signal of the above-mentioned captured signal level is output, and a read/write control signal ' to be transmitted to the gates of _MOSFETQ13 and _Q14 is
form.

This operation will be explained according to the timing diagram of FIG.

In the case of a write operation, the multiplexed signal / _Dio is brought to a low level before the chip selection signal falls. Therefore, by setting the chip selection signal to low level, _MOSFETQ15
When the MOSFET Q 15 is turned off, the low level signal just before the MOSFET Q ₁₅ is turned off is held at the input side of the latch circuit F/F. Next, input buffer circuit
When the internal chip selection signal CS obtained via BA is changed to a high level in response to the change of the chip selection signal CS from the outside to the low level, the latch circuit F/F is thereby activated. As a result, in synchronization with the rising edge of the internal chip selection signal CS,
The latch circuit F/F outputs a high level signal WE' which is the opposite level to the signal level held at its input side.

Therefore, MOSFETQ ₁₃ and Q ₁₄ turn on,
The output terminal of the write circuit 6 and the common data line CD are connected. At this time, if the multiplexed signal WE/Din is used as write data as it is, that is, if the multiplexed signal WE/Din is left at a low level as shown in the broken line waveform in FIG. ”) is written. On the other hand, when the multiplexed signal WE/Din is changed to a high level as shown in the solid line waveform in Fig. 3,
Writing of high level (“1”) is performed.

That is, in the same figure, when the multiplexed signal is changed to a high level for a predetermined period of time before the end of the write operation cycle, as shown by the solid line, "1" writing is performed, and as shown by the dotted line in the figure. If it remains low level, "0" is written.

Note that during reading, the multiplexed signal WE/Din remains at a high level when the chip selection signal CS falls, so the latch circuit F/Din remains at a high level.
The signal WE' formed by F remains at a low level. MOSFETQ ₁₃ , Q ₁₄ accordingly
is never turned on, so a normal read operation is performed.

In this embodiment, when writing, as described above, "0" is first written, and "1" is written later, so that "1" is finally written. Since the time required for writing is short, there is no problem since there is sufficient time to perform the above-mentioned writing twice between the operation cycles defined by the read operation time.

Therefore, by multiplexing the signals in time series, the number of external terminals can be reduced.

This allows the storage capacity to be doubled under the same external terminal. That is, under the same number of external terminals, the external terminals that are no longer needed as a result of the above multiplexing can be used, for example, as address input terminals. By changing the external terminals in this manner, the address signal can be increased by one bit, thereby doubling the range of memory addresses that can be specified. In other words, by increasing the address range that can be specified, the storage capacity can be doubled. On the other hand, when the number of external terminals is reduced by the above-mentioned multiplexing, the number of external terminals can be reduced and the device can be mounted in a smaller package with the same storage capacity. Furthermore, by reducing the number of external terminals, the number of bonding pads that require a relatively large area can be reduced, making it possible to increase the density of the IC chip. Furthermore, there are various advantages such as a reduction in assembly man-hours such as wire bonding.

The invention is not limited to the above embodiments.

The timing signal for sampling and holding the multiplexed read/write control signal may be formed based on the address signal.

Further, the write data may also be obtained by sampling at an appropriate timing in the same manner as described above.

The present invention can be similarly applied to static type RAMs composed of bipolar transistors as well as MOS static type RAMs.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a MOS static RAM showing one embodiment of the present invention, Fig. 2 is a circuit diagram showing its main part in one embodiment, and Fig. 3 is a timing chart for explaining its operation. It is a diagram. 1...Memory array, 2...X address decoder circuit, 3...Y address decoder circuit, 4...
Sense amplifier, 5... Output buffer circuit, 6...
Write circuit, 7...control circuit, 8...external power supply device.

Claims (1)

[Scope of Claims] 1. A memory array including a plurality of memory cells, a word line, and a data line, a first address decoding circuit that decodes an input address signal and selects the word line, a common data line, and the above-mentioned memory array. a column switch provided between the data line and the common data line; a second address decoding circuit that decodes the input address signal and controls the column switch; and a sense sensor having an input terminal connected to the common data line. a readout circuit consisting of an amplifier and an output buffer circuit to which the output of the sense amplifier is supplied, the operation of which is controlled by a first control signal for chip selection from an external terminal, and input data from the outside. a write circuit that receives a signal; a first gate means whose operation is controlled by a second control signal for write control so that an output of the write circuit is applied to the common data line; A random access memory comprising a circuit, wherein the external terminal for receiving the input data signal and the external terminal for receiving the second control signal are a common external terminal, and A control circuit is operationally controlled by the first control signal supplied via the external terminal, and controls the signal at the common external terminal when the first control signal changes from a chip non-selection level to a chip selection level. It comprises a second gate means for sampling, and a latch circuit activated by the chip selection level of the first control signal to take in the sampling signal from the second gate means, and the output of the latch circuit is A random access memory characterized in that the second control signal is supplied to the first gate means.