JPH10134565A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To protect data in the memory cells of columns other than a writing object from breakdown at the time of writing by a method wherein writing word signals are supplied only to 3-transistor memory cells belonging to a column selected by a column selection signal. SOLUTION: Writing word signals are not supplied to all memory cells 40 but supplied only to memory cells 40 belonging to a selected column. That is, a double-word signal is generated by the logical product of the writing word signal and a column selection signal. Therefore, data are written only in the memory cells 40 belonging to the column which is the object of data writing and the writing word signals are not supplied to the memory cells 40 belonging to the other columns. As a result, data in the memory cells belonging to the columns other than the writing object are protected from breakdown.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor memory device. In particular, it relates to a semiconductor memory device using a three-transistor memory cell.

[0002]

2. Description of the Related Art Various memory cells are used in semiconductor memory devices. For example, a static ram (hereinafter, referred to as SRAM) using six transistors, or a dynamic ram (hereinafter, referred to as DRAM) that forms one memory cell with one transistor and one capacitor.
Etc. are used. A DRAM has a smaller number of transistors than an SRAM, and thus is widely used for forming a large-capacity semiconductor memory device. However, a refresh operation for retaining stored contents is required.

In recent years, an ASIC using a gate array or the like has been widely used, but the ASIC is often formed by a CMOS process from the viewpoint of power consumption and the like. In the ASIC, a circuit for a specific application can be freely configured, and, for example, a CPU core and a memory are often built therein. As a memory built in the ASIC, a so-called three-transistor type memory cell is often used. According to the SRAM described above, the refresh operation is unnecessary, but one memory cell requires as many as six transistors. On the other hand, when a DRAM is mounted, a special DRAM process is required, and there is a problem that it is difficult to use an ASIC formed by a general CMOS process.

For this reason, an ASIC formed by a normal CMOS process uses a so-called three-transistor type memory cell. FIG. 2 shows a circuit diagram of the three-transistor type memory cell.

As shown in FIG. 2, this three-transistor type memory cell has a write transistor 10
, Storage transistor 12 and read transistor 1
4.

First, when writing data to the three-transistor type memory cell, data to be written is applied to a write bit line (WBL). Next, the write word line (WWL) is set to “H” level, and the write transistor 10 is turned on. Then, the write bit line (WB
L) is the content of the data appearing in the storage transistor 12.
Is applied to the gate. In this state, the write transistor 10 is turned off by setting the write word line (WWL) to “L”. Then, data on the write bit line (WBL) is stored as a charge in the gate terminal of the storage transistor 12.

[0007] Data stored in the gate terminal of the storage transistor 12 as electric charge can be read depending on whether the storage transistor is in a conductive state or a non-conductive state. Therefore, the data is read to the read bit line (RBL) via the read transistor 14 connected to the storage transistor 12. To read data to the read bit line (RBL), the read word line (RWL) is set to “H”. Then, the read transistor 14 becomes conductive, and data corresponding to the charge stored in the gate terminal of the storage transistor 12 is read.

Specifically, when "H" is applied to the gate terminal of the storage transistor 12, a predetermined charge is charged to the gate terminal, and the storage transistor 1
2 is a conduction state. Therefore, the read transistor 1
4, the data read out to the read bit line (RBL) becomes “L”. On the other hand, when a potential of “L” is applied to the gate terminal of the storage transistor 12,
The storage transistor 12 is off, and a value of “H” is read to the read bit line (RBL). Therefore, data having the opposite polarity to the charge applied to the gate terminal is read.

FIG. 3 is a block diagram showing the configuration of a semiconductor memory device using a three-transistor type memory cell as described in FIG. The semiconductor memory device shown in FIG. 3 is used for a FIFO memory or the like.

The address supplied to the semiconductor memory device is supplied to a write column decoder 20 and a read column decoder 26. The upper bits of the address are supplied to these two types of column decoders. The lower bits of the address are supplied to the write word decoder 22 and the read word decoder 24, respectively.

The write column decoder 20 outputs a predetermined column select signal based on the input address. Then, one of the light column selectors 0 to n-1 is set to the operation state. The write column decoder 20 receives an upper address signal and a write control signal, and operates by selecting one of the column selectors 0 to n-1 when data is written to the semiconductor memory device. State it.

As described above, when data is written, the write column selector 0 to the write column selector n-1 are used.
Is in the operating state, and the write word decoder 22 operates based on the upper address and the write control signal.
A write word signal is output to the write word line. The data to be written is supplied from the input terminal to the write driver 32 via the input circuit 30.

The data width of the semiconductor memory device is m bits, and the input circuit 30 and the write driver 32 are also composed of m bits. The m-bit data output from the write driver 32 has a write data bus (WDB) <0:
m-1> to the respective light column selectors 0 to n-1. The data to be written via the write column selector selected by the write column decoder 20 is the write bit line (WB
L <0: m-1>).

Next, when the write word signal generated by the write word decoder 22 becomes "H", predetermined data is written to the corresponding memory cell 40.

On the other hand, when data is read, the read column decoder 26 operates instead of the write column decoder 20. This read column decoder outputs predetermined column select signals (RY0 to RYn-1) and selects one of the read column selectors 0 to n-1.

When reading data, the read word decoder 24 outputs a read word signal to a read word line (RW
L). Then, the memory cell 4 at the corresponding position
The content written to 0 is the read bit line (RBL)
Is read out. The read data is received by the sense amplifier 42, and the read column selector 0
To the sense amplifier 44 via any one of the read column selectors n-1. These read column selectors 0 to n-1 are connected to the sense amplifier 44 via a read data bus (RDB) <0: m-1>. This sense amplifier 44 is also connected to the input circuit 30 and the write driver 32.
The data read out by the sense amplifier 44 is output to the data output terminal via the output circuit 46 in the same manner as described above.

[0017]

A conventional semiconductor memory device using a three-transistor type memory cell as shown in FIG. 3 performs data writing and data reading as described above. Therefore, when writing data, all the cells connected to the write word line (WWL) whose write word signal is “H” are activated, that is, the data is written. However, the data to be written is one of the write column selectors (0 to n-1).
), No predetermined data is applied to the memory cells connected to the other write column selectors. As a result, data in memory cells not subjected to the write operation is destroyed.

Therefore, in a conventional semiconductor memory device using a three-transistor type memory cell as shown in FIG. 3, when data is to be written,
First, it is necessary to read out all the contents of all the memory cells connected to one write word line (WWL) and store them in an external buffer.

FIG. 4 is a timing chart showing the operation when reading and writing data in such a conventional semiconductor memory device. As shown in the timing chart, it is necessary to temporarily write data to the buffer during the data write operation, and the data write time is significantly longer than the data read time.

As described above, in a conventional semiconductor memory device using a three-transistor type memory cell, complicated control is required at the time of writing data, and the access speed is slow.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to prevent data in a memory cell other than a write target from being destroyed at the time of data writing in a semiconductor memory device using three-transistor memory cells. An object of the present invention is to provide a semiconductor memory device.

[0022]

According to the present invention, there is provided a semiconductor memory device using three-transistor type memory cells, which decodes an address and generates a column selector signal. A write word decoder that decodes an address and a write control signal to generate a write word signal; and a logical product of the write word signal and the column selector signal to generate a double word signal; And an AND gate for supplying the write word signal to only the three-transistor memory cells belonging to a column selected by the column selector signal. It is a semiconductor storage device.

Since data is written only to the memory cells in the column to be written, data in other memory cells not to be written is not destroyed.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to a preferred embodiment of the present invention.

The configuration of the semiconductor memory device shown in FIG. 1 is almost the same as that of the conventional semiconductor memory device shown in FIG. The configuration shown in FIG. 1 differs from FIG. 3 in that an AND gate 50 is provided for each column. And each column (0
The memory cells 40 belonging to n-1) output the output signal of the AND gate 50 provided for each corresponding column to a word write signal (this is called a double word signal).
It is received as. The AND gate 50 outputs a write word signal (appearing on the write word line (WWL)) which is an output signal of the write word decoder 22 and a column select signal WY (0 to n-1) which is a signal for selecting a column to which the write word signal belongs. ) And outputs it as a double word signal.

A feature of this embodiment is that the write word signal is not directly supplied to all the memory cells 40, but the write word signal is logically ANDed with the column select signals WY0 to WYn-1. Is taken, each memory cell 4 (as a double word signal)
It is supplied to zero.

As described above, in this embodiment, the write word signal is not supplied to all the memory cells 40 but is supplied only to the memory cells 40 belonging to the selected column. Therefore, data is written only to the memory cells 40 of the column to which data is to be written, and no write word signal is given to the memory cells 40 belonging to the other columns, and no write operation is performed. As a result, data in memory cells other than the memory cell in the column to be written is not destroyed.

Therefore, according to the present embodiment, there is no need to perform complicated control such as reading out data in advance to prevent data destruction when writing data. Note that the semiconductor memory device shown in FIG. 1 performs the same operation as the semiconductor memory device shown in FIG.

FIG. 5 is a timing chart showing the operation when reading and writing data in the semiconductor memory device according to the present embodiment. As shown in this timing chart, at the time of the data write operation, unlike the operation shown in FIG. 4, it is not necessary to write the data into the buffer once. Therefore, the data writing time can be set to be the same as the reading time.

As described above, in the present embodiment, AN is connected between the word write line (WWL) and each memory cell 40.
Since the D gate 50 is provided, the time required for the write word signal to reach the actual memory cell 40 may be increased by one gate. However, in the conventional configuration shown in FIG. 3, the load of the write word decoder 22 is considerably large because the word write line (WWL) is connected to the memory cells 40 of all the columns. By contrast, in the configuration shown in FIG. 1, the load of the write word coder 22 is greatly reduced because the write word decoder 22 only needs to drive only n AND gates 50. Therefore, it is expected that the rise of the write word signal in the word write line (WWL) is considerably faster in the configuration shown in FIG. 1 than in FIG. for that reason,
Even if a delay of one stage occurs due to the AND gate 50, the circuit configuration shown in FIG. 1 is not considered to be significantly disadvantageous as compared with the circuit configuration shown in FIG.

[0032]

As described above, according to the present invention, the write word signal is ANDed with the column select signal to generate a double word signal. Then, a double word signal is supplied to a three-transistor memory cell which is a memory cell. Therefore, since the data of the memory cells belonging to the columns other than the data write target are not destroyed, it is possible to provide a semiconductor memory device in which control at the time of data write is simple.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a semiconductor memory device according to a preferred embodiment of the present invention.

FIG. 2 is a circuit diagram of a three-transistor type memory cell.

FIG. 3 is a configuration block diagram of a conventional semiconductor memory device.

FIG. 4 is a timing chart showing data read and write operations of a conventional semiconductor memory device.

FIG. 5 is a timing chart illustrating data read and write operations of the semiconductor memory device according to the present embodiment.

[Explanation of symbols]

20 write column decoders, 22 write word decoders, 24 read word decoders, 26 read column decoders, 30 input circuits, 32 write drivers,
40 memory cells, 42 sense amplifiers, 44 sense amplifiers, 46 output circuits, 50 AND gates.

Claims (1)

[Claims] In a semiconductor memory device using three-transistor memory cells, a column address decoder for decoding an address and generating a column selector signal and a write for decoding an address and a write control signal and generating a write word signal are provided. A logical product of a word decoder, the write word signal, and the column selector signal is generated to generate a double word signal, and the double word signal is supplied to the three-transistor memory cell.
An ND gate, and only the three-transistor type memory cells belonging to the column selected by the column selector signal,
A semiconductor memory device to which the write word signal is supplied.