JPH05250872A - Random access memory - Google Patents

Abstract

PURPOSE:To reduce the power consumption at the time of the output of a RAM having the I/O terminal of multi-bit. CONSTITUTION:Not only an input controlling transfer gate 60 is operated on/off based on an output signal WC1-0 outputted from an access control circuit 90 at the time of the fall of a RASN but also an output controlling transfer gate 70, as well is operated on/off by using the output signal WC1-0 effectively. By the transfer gate 70, only the read data of an optional bit is outputted from an output buffer 50 to the I/O terminal 100 and the power consumption at a data reading operation time is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a random access memory (hereinafter referred to as RAM) having multi-bit input / output (hereinafter referred to as I / O) terminals, and in particular, output control during a write per bit mode operation. It is about.

[0002]

2. Description of the Related Art Conventionally, an RA having a multi-bit I / O terminal
As a technique relating to M, for example, JP-A-60-1799
There is one described in Japanese Patent Publication No. 84. FIG. 2 is a block diagram showing a configuration example of a RAM having a conventional multi-bit I / O terminal described in the above document. This RAM is a multi-address type memory that uses a row control signal RAS _N (where N means an opposite phase) and a column control signal CAS _N , and is an address supplied from outside controlled by the row control signal RAS _N. A row address buffer 1 for taking in row addresses from A ₀ , A ₁ , ..., A _n is provided, and a memory cell array 3 is connected to an output side thereof via a row address decoder 2. The row address decoder 2 is a circuit that decodes the output of the row address buffer 1. The memory cell array 3 has a plurality of word lines WL and a plurality of bit line BL pairs arranged so as to intersect therewith, and a MOS is provided at each intersection.
A memory cell 3a made of a transistor is connected, and a sense amplifier (not shown) for detecting and amplifying read data from the memory cell 3a is connected to each bit line BL pair.

[0003] The address A ₀ is controlled by a column control signal CAS _N, A _1, ..., the column address buffer 4 is provided for taking the column address in A _n, to its output side, the column decoder 5 and the transfer The memory cell array 3 is connected via the gate circuit 6. The column decoder 5 is a circuit that decodes the output of the column address buffer 4.
The transfer gate circuit 6 receives, for example, four sets of bit lines B in the memory cell array 3 based on the output of the column decoder 5.
L pairs and four pairs of I / O bus lines 7 ₀ , 7 ₁ , 7 ₂ , 7 ₃
It is composed of a plurality of switches for controlling conduction / non-conduction with and.

Each I / O bus line 7 ₀ , 7 ₁ , 7 ₂ , 7
_3, together with the data amplifier 8 for amplifying a difference signal on the I / O bus lines _0, 8 _1, 8 _2, 8 ₃ are respectively connected, I / O buffer circuits 9 _0, 9 _1, 9 ₂ , 9 ₃
Are connected respectively. Each I / O buffer circuit 9 ₀ , 9 ₁ , 9 ₂ , 9 ₃ has an I / O terminal 10 ₀ , 10 ₁ , 1 for inputting / outputting write data and read data.
0 ₂ and 10 ₃ are connected. Next, a data write operation to the memory cell array 3 and a data read operation from the memory cell array 3 will be described. When data is read from the memory cell array 3, addresses A _{0 to} A _n are externally supplied to the row address buffer 1 and the column address buffer 4. Then, the row address buffer 1 controlled by the row control signal RAS _N causes the address A ₀
To A _n row address is taken from the preparative incorporated row address is decoded by row address decoder 2, one word line WL of the memory cell array 3 is activated.
When one word line WL is activated, stored data is read from the plurality of memory cells 3a connected thereto and output to the plurality of bit line BL pairs. Each bit line BL
The data read to the pair is amplified by a sense amplifier (not shown).

On the other hand, the column address buffer 4 controlled by the column control signal CAS _N fetches the row address from the addresses A _{0 to} A _n , and the fetched row address is decoded by the column decoder 5. As a result of this decoding, four sets of switches in the transfer gate circuit 6 are turned on, and the four sets of bit line BL pairs selected by the column decoder output and the four sets of I / O bus lines 7 _{0 to} 7 ₃ are conducted. , Read data on the four pairs of bit lines BL is I / O.
It is output to the bus line 7 _{0-7 3.} I / O read data on the bus line 7 _{0-7 3,} data amplifier 8 _0-8
After being amplified by _3, it is outputted from the I / O terminal 10 _{0 -} 10 ₃ via the I / O buffer circuits 9 _{0-9 4.}

[0006] When writing data, when supplying data to be written to I / O pins 10 _{0 -} 10 _3, it is incorporated into the I / O buffer circuits 9 ₀ to 9 ₄ I / O bus lines 7 _{0 to} 7 ₃ . Then, four sets of switches of the transfer gate circuit 6 is turned on by the output of the column decoder 5, the four sets of I / O bus line 7 _{0-7 3} 4 pairs of the memory cell array 3 of the bit line BL pairs Data is written to the memory cell 3a which is conductive and connected to the intersection of the word line WL selected by the row address decoder 2 and the four pairs of bit BL pairs. Figure 3
Is a circuit diagram of the I / O buffer circuits 9 ₀ shown in FIG. This I / O buffer circuit 9 ₀ has the same circuit configuration as the other I / O buffer circuits 9 _{1 to} 9 ₃ and has an I / O terminal 10 _0.
The input buffer 21 connected between the I / O bus line 7 ₀ and the I / O bus line 70, and the I / O bus line 7 ₀ and the I / O terminal 10 _0.
And an output buffer 22 connected between and. Between the input buffer 21 and the I / O bus lines 7 _0, input control transfer gate 23 for controlling conduction / non-conduction of both of them are connected. The transfer gate 23 is on / off controlled by the output of a write inhibit register 24 which is an access control circuit. The write inhibit register 24 is composed of a write inhibit sensing circuit 24A and a buffer 24B.

FIG. 4 is a circuit diagram showing a configuration example of a control signal generation circuit for generating various control signals of FIGS. 2 and 3. In the control signal generation circuit 30, the row control signal RAS
_N is inverted by the inverter 31 ₁ to become the signal RAS,
It is sequentially driven by the buffers 32 ₁ , 32 ₂ , 32 ₃ , 32 ₄ to become signals RAS ₁ , RAS ₂ , RA, SE. Further, the signal RAS is inverted by the inverter 31 ₂ to become the precharge signal PX ₀ , which is the buffer 32.
It is inverted at ₅ to become the precharge signal PX ₁ . The word line activation signal RA and the inverted signal of the column control signal CAS _N are logically ANDed by the AND gate 33 ₁ to obtain the signal CAS.
And the signal CAS becomes the buffers 33 ₂ , 33 ₃ , and 3.
The signals CAS ₁ and CA are sequentially driven by 3 ₄ and 33 _5.
S ₂ , RE, OE ₁ . Further, the signal CAS is inverted by the inverter 34 to become the precharge signal PY ₀ ,
The precharge signal PY ₀ is driven by the buffer 33 ₆ and becomes the precharge signal PY ₁ . Further, the inversion signal of the precharge signal PY _{1 and} the inversion signal of the write control signal WE _N are ANDed by the AND gate 35 and become the signal W ₀ , and the signal W ₀ is driven by the buffer 36 and the signal W _0. Becomes ₁ .

In FIG. 3, REF in the input buffer 21 is a reference signal and WC ₀ in the write inhibit register 24.
-0 is an output signal of the write inhibit sensing circuit 24A, WC ₁ −
0 is the output signal of the buffer 24B. FIG. 5 is a timing chart of FIGS. 2 and 3, and the operation of FIG. 3 will be described with reference to this figure. In the read operation, the signal W ₁
The input buffer 21 is deactivated by the write control signal W
Since write inhibit sensing circuit 24A is inactive, and the input control transfer gate 23 by the output signal WC ₁ -0 buffer 24B is off by E _N, the read data on any bit line BL pairs I / O bus lines It is output to 7 _0, I / O terminal 1 thereby output buffer 22
It is output from 0 ₀ to the outside.

In the write operation, the write inhibit sensing circuit 24
A is row control signal RAS and the write control signal WE _N during the fall of the _N, I / O level of the terminal 10 ₀ and column control signals C
The write cycle is identified by two combinations with the level of the write control signal WE _N after the fall of AS _N , and the output signal WC ₀ -0 is driven by the buffer 24B. The output signal WC ₁ -0 buffer 24B
Then, the input control transfer gate 23 is turned on and data is written. That is, when the row control signal RAS _N falls, the write control signal WE _N and the I / O terminal 10 ₀ are set to the “L” level, so that the write inhibit sensing circuit 2
The output signal WC ₀ -0 of 4A becomes "H" level, it is driven by the buffer 24B, the transfer gate 23 is turned on by the output signal WC ₁ -0 of the "H" level. As a result, the output side of the input buffer 21 and the I / O
Bus line 7 ₀ and is rendered conductive, thereby enabling normal write operation.

[0010] row control signal RAS _N falling when the write control signal WE _N "L" level, when the "H" level to the I / O terminal 10 _0, the output signal WC of the buffer 24B
₁ -0 is to maintain the "L" level. When the output signal WC ₁ -0 buffer 24B becomes "L" level, the transfer gate 23, a state in which the input buffer 21 is disconnected from the I / O bus lines 7 _0, even if entering the write cycle, I / O bus lines 7 _0, the bit line BL pairs, and writing data into the memory cell 3a is prohibited. For example, the write inhibit register 2 shown in FIG.
When 4 is not provided, in order to write only arbitrary bits, the read-modify-write function can be used by unnecessarily writing once read data. However, there are drawbacks such as read-modify-write, which can be used only at a specific timing, and writing which may not be performed is necessary, which increases power consumption.

[0011] Therefore, in the literature of the art, providing a write inhibit register 24 shown in FIG. 3, by the function of the write-inhibit register 24 and transfer gate 23, RAM with I / O pins 10 _{0 -} 10 ₃ multibit in has been achieved without the independent writing / reading control of the I / O pins 10 _{0 -} 10 every _3, impairing inherent memory function.

[0012]

However [0007] In the RAM of the above-described configuration, an independent writing / reading control of the I / O pins 10 _{0 -} 10 every _3, although can be realized without impairing the inherent memory function, order to diversify the operation mode, when using a specific timing, such as a read-modify-write, to perform an unnecessary data output also to the I / O terminal 10 _{0 -} 10 ₃ not to perform the write operation become. Therefore, there arises a problem that the power consumption at the time of output increases, and it is difficult to solve it.

The present invention provides a RAM having a multi-bit I / O terminal, which solves the problem that the power consumption at the time of output increases as the problem of the prior art.

[0014]

In order to solve the above problems, the present invention provides a plurality of I / O bus lines for transmitting write data and read data to / from a memory cell and each of the I / O bus lines. The write data connected to and input from the I / O terminal is sent to the I / O bus line, and the write data on the I / O bus line is transferred to the I / O.
In a RAM having a plurality of I / O buffer circuits for outputting to terminals and controlling the write operation to the memory cells by a write control signal, each I / O buffer circuit is configured as follows. That is, each I / O buffer circuit drives the write data input from the I / O terminal and sends the write data to the I / O bus line, and the write data on the I / O bus line. An output buffer for driving the I / O terminal to output to the I / O terminal; an input control transfer gate for connecting / disconnecting between the input buffer and the I / O bus line;
An output control transfer gate for connecting / disconnecting the O bus line and the output buffer and an access control circuit are provided. The access control circuit identifies a write / read cycle based on the write control signal at the time of falling or rising of the control signal and the level of the I / O terminal, and at the time of the write cycle, the input control transfer gate is used. It has the function of bringing the output control transfer gate into the conductive state during the read cycle.

[0015]

According to the present invention, as described above, the multi-bit I
Since the RAM I / O buffer circuit having the / O terminal is configured, an output signal is output from the access control circuit when the control signal falls or rises, and the input control transfer gate is turned on and off based on the output signal. In addition to operating, the output control transfer gate also turns on and off. By turning the output control transfer gate on and off, only the read data of an arbitrary bit can be output from the output buffer, and the power consumption during the data read operation can be reduced. Therefore, the above problem can be solved.

[0016]

DETAILED DESCRIPTION FIG. 1 is a circuit diagram of the I / O buffer circuits 9 ₀ showing an embodiment of the present invention. This I / O buffer circuit 9
₀ is provided in the conventional RAM shown in FIG. 2, and the other I / O buffer circuits 9 _{1 to} 9 ₃ in the RAM have the same circuit configuration.

[0017] I / O buffer circuits 9 ₀ is composed similarly MOS transistor and the conventional FIG. 3, I / O pin 10
₀ and the I / O bus line 7 ₀ , the input buffer 40, the I / O bus line 7 ₀ and the I / O terminal 10
And an output buffer 50 connected between ₀ and ₀ . Between the I / O bus lines 7 ₀ and the input buffer 40, the transfer gate 60 is connected for input control, between the I / O bus lines 7 ₀ and the output buffer 50, output control transfer The gate 70 and the equalize circuit 80 are connected. The input control transfer gate 60, the output control transfer gate 70, and the equalize circuit 80 are controlled to be turned on and off by an access control circuit 90. The access control circuit 90 includes a write inhibit sensing circuit 100 and a buffer 1
It is composed of 10.

The input buffer 40 is precharged by the precharge signal PY ₁ as in FIG.
A circuit activated by a signal W ₁ and a reference signal R
Input transistor 41 that is turned on and off by EF
When, a ON, an input transistor 42 off operation by writing data from the I / O pins 10 _0. Signal input from the input transistors 41 and 42, the transistor is amplified by 43, 44, 45, 46, I / O terminals 10 ₀ Write data from is converted into complementary signals input control transfer gate 60 To be sent to. The output buffer 50, similarly to FIG. 3, it is precharged by the precharge signal PY _1, a circuit which is activated by the signal OE _1. In the output buffer 50 receives complementary signals from I / O bus lines 7 ₀ at the input transistors 51 and 52,
On the output transistors 57 and 58 and differential amplifier with transistors 53, 54, 55, 56, by turning off operation, the I / O bus lines 7 by driving the read data on the ₀ I / O pin 10 ₀ It has a function to output to.

The input control transfer gate 60 is turned on by the output signal WC ₁ -0 access control circuit 90 is composed of a pair of transistors 61 and 62 off operation, the output side of the input buffer 40 by the transistors 61 and 62 It has a function of the conduction / non-conduction between the I / O bus lines 7 _0. The output control transfer gate 70 outputs the output signal WC ₁ of the access control circuit 70.
A pair of transistors 7 that are turned on and off by -0
It is composed of 1,72, and has a function of the conduction / non-conduction of the input side of the I / O bus lines 7 ₀ and the output buffer 50 by the transistors 71 and 72.

The equalizing circuit 80 is constituted by the I / O bus lines 7 ₀ connected between the two signal lines constituting the transistors 81, the output signal WC ₁ -0 inverter 7
And the transistor 81 is inverted by the inverted signal.
Has a function of making the two signal lines have the same level when the output is disabled by turning on and off. The access control circuit 90 is composed of a write inhibit sensing circuit 100 and a buffer 110, like the write inhibit register 24 of FIG. Write protect sensing circuit 1
00 has a function to identify the write cycle / read cycle by the row control signal RAS _N falling time of the write control signal WE _N and I / O pins 10 ₀ level sensing a write-protected. This write inhibit sensing circuit 100
It includes a transistor 101 and 102 of the pull-up on the word line activation signal RA, on the off operation to the transistor 103, I / O terminals 10 ₀ level, the transistor 104 to OFF operation, the row control signal RA
A transistor 105 that is turned on and off by S _N ,
And a transistor 106 that is turned on and off by the write control signal WE _N. The transistors 103, 104, 105 and 106 constitute a 4-input NOR gate, and the output signal WC _0-0 thereof is the buffer 11.
Sent to 0.

The buffer 110 is a write inhibit sensing circuit 1
The output signal WC ₀ -0 00 by driving and has a function of outputting an output signal WC ₁ -0 which is driving the transfer gates 60, 70 and the equalizer circuit 80. This buffer 110 is precharged by the precharge signal PX ₁ and outputs the output signal WC of the write inhibit sensing circuit 100.
_0-0 is input from the input transistors 111 and 112,
It has a circuit configuration for outputting an output signal WC ₁ -0 from the output transistors 113 and 114 to drive the input. FIG. 6 is a timing chart showing the operation of FIGS. 1 and 2. Each control signal shown in FIG. 1 is generated from the conventional control signal generating circuit 30 shown in FIG. With reference to FIG. 6, the operation of the RAM 2, including the I / O buffer circuits 9 ₀ in FIG.

First, the write operation will be described. In the write operation, as in the conventional case, the write inhibit sensing circuit 100 causes the write control signal WE at the fall of the row control signal RAS _N.
N and, I / O level of the terminal 10 ₀ and column address strobe signal CAS
_The write cycle is identified by a combination of the two depending on the level of the write control signal WE _N after the fall of _N. During the falling of the row control signal RAS _N, the write control signal WE by the _N and I / O pin 10 ₀ "L" level, the output signal WC ₀ of write inhibit sensing circuit 100 -
0 is driven by the buffer 110, and its output signal WC ₁ −
0 becomes "H" level. Output signal WC ₁ -0 is "H"
When the level is reached, the input control transfer gate 60 and the output control transfer gate 70 are turned on. At this time, the output buffer 50 is inactivated by the signal OE ₁ . On the other hand, since the input buffer 40 is activated by the signal W ₁ , the I / O terminal 10 ₀
Write data input from is converted into complementary signals in the input buffer 40, it is sent through the input control transfer gate 60 to the I / O bus lines 7 _0. Write data sent to the I / O bus line 7 _0,
As in the conventional case, the data is written in the memory cell 3a via the transfer gate circuit 6 of FIG.

Next, the read operation will be described. In the operation at the time of reading, the row control signal RAS _N falling time of the write control signal WE _N is "L" level, and the I / O terminal 10
When ₀ is at "L" level, the output signal WC ₁ -0 access control circuit 90 becomes the "H" level, the transfer gate 70 is turned on for the transfer gate 60 and the output control input control, the equalizer circuit 80 within Transistor 81 turns off. At this time, the input control transfer gate 60 is turned on, but the input buffer 40 is deactivated by the signal W ₁ . When the column control signal CAS _N falls, the output buffer 50 is activated by the signal OE ₁ output from the control signal generation circuit 30 of FIG. Therefore, through the output control transfer gates 70, the read data on the I / O bus lines 7 ₀ is driven by the output buffer 50, the output transistor 5
The read data corresponding to the potential difference on the I / O bus line 7 ₀ is output from the I / O terminal 10 ₀ via 7, 58.

On the other hand, when the row controlled by a signal RAS _N of fall-time write control signal WE _N is "L" level, and I / O pins 10 ₀ is at "H" level, the access control circuit 9
To maintain the output signal WC ₁ -0 is "L" level of 0, turns off the output control transfer gate 70, transistor 81 of the equalizing circuit 80 is turned on, constituting the I / O bus lines 7 ₀ The potentials of the two signal lines are at the same level. Therefore, the column control signal CAS _N
It is but down standing, not transmitted signals of the I / O bus lines 7 ₀ to the output buffer 50, and since the two input lines of the output buffer 50 becomes the same level, I / O pins 10 ₀
No read data is output to.

[0025] As described above, in this embodiment, I / O between the bus line 7 ₀ and the input side of the output buffer 50, is provided with the output control transfer gates 70, the multi-bit I / O pin in RAM with 10 _{0 -} 10 _3, the transfer gate 70 by the output signal WC ₁ -0 access control circuit 90 on, by turning off the control, only I / O pins 10 _{0 -} 10 ₃ of an arbitrary bit Read data can be output. Therefore, the current consumption during the read operation can be reduced.

The present invention is not limited to the above embodiment,
Various modifications are possible. Examples of such modifications include the following. (A) In the above embodiment, the case of 4-bit I / O terminals 10 ₀ to 10 ₃ has been described as shown in FIG. 2, but they may have an arbitrary number of bits. (B) an input buffer 40 of the I / O buffer circuits 9 ₀ in FIG. 1, the output buffer 50, the transfer gates 60,77, the equalizing circuit 80 and the access control circuit 90, is or constructed using other transistors Alternatively, a circuit configuration other than that shown may be changed.

[0027]

As described in detail above, since the transfer gate for output control controlled by the output of the access control circuit is provided between the I / O bus line and the input side of the output buffer, multi-bits are provided. RA with I / O terminal
In M, not only the transfer gate for input control but also the transfer gate for output control can be controlled by using the control signal output from the access control circuit, so that only the read data of any bit is read by the transfer gate for output control. Can be output from the I / O terminal. for that reason,
Power consumption during the read operation can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an I / O buffer circuit provided in a RAM having multi-bit I / O terminals according to an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a conventional RAM.

FIG. 3 is a circuit diagram of the I / O buffer circuit of FIG.

FIG. 4 is a circuit diagram of the control signal generation circuit of FIGS. 2 and 3.

FIG. 5 is a timing chart showing the operation of FIGS. 2 and 3.

FIG. 6 is a timing chart showing the operation of FIGS. 1 and 2.

[Explanation of symbols]

1 row address buffer 2 row address decoder 3 memory cell array 4 column address buffer 5 column decoder 6 transfer gate circuit 9 _{0 to} 9 ₄ I / O buffer circuit 10 ₀ to 10 ₃ I / O terminal 40 input buffer 50 output buffer 60 input control Transfer gate 70 Output control transfer gate 80 Equalize circuit 90 Access control circuit 100 Write inhibit sensing circuit 110 Buffer

Claims (1)

[Claims] 1. A plurality of input / output bus lines for transmitting write data and read data to a memory cell,
The write data connected to each of the input / output bus lines and input from the input / output terminal is sent to the input / output bus line, and the write data on the input / output bus line is output to the input / output terminal. A plurality of input / output buffer circuits for controlling a write operation to the memory cell by a write control signal, wherein each input / output buffer circuit receives an input from the input / output terminal. An input buffer for driving the write data to be sent to the input / output bus line; an output buffer for driving the write data on the input / output bus line to output to the input / output terminal; An input control transfer gate for connecting / disconnecting between a buffer and the input / output bus line, the input / output bus line and the output An output control transfer gate to conduction / non-conduction between the Ffa, based on the level of the write control signal falling at or during the rise, and the entering / output terminal of the control signal, the write /
An access control circuit for identifying a read cycle, bringing the transfer gate for input control into a conductive state during a write cycle, and bringing the transfer gate for output control into a conductive state during a read cycle; Access memory.