JPH023164A - Dual port memory - Google Patents

Abstract

PURPOSE:To inhibit erroneous writing from other port with a simplified circuit constitution by providing a writing control circuit to set an area inhibiting the writing of the port of a remote side to one port at a dual port memory which shares one memory cell and has two address data input ports independent each other. CONSTITUTION:When one memory cell 7 is shared and writing control is executed to a remote port each other, the output of a writing control circuit 1 of a left side port is impressed to a negative logic NAND gate 9 of a right side port. Besides, a chip selecting signal the inverse of CSR is given to the gate 9 separately, when a output WER is a high level, writing is allowed, and when it is a low level, the writing is inhibited. Besides, the output of a writing control circuit 8 of the one right side port is impressed to a negative logic NAND gate for writing 2 of the left side port, the chip selecting signal the inverse of CSR is govern to the gate 2. Then, data to which the writing is allowed by the respective gates 2 and 9 are processed by I/O buffers 4, 11 and so on.

Description

[Detailed Description of the Invention] The present invention has one memory cell, two completely independent addresses, and data input/output ports, and data can be sent from each port to any address of the memory cell. This is a dual-port memory that can read and write data.

In recent years, with the development of digital signal technology, various types of memories have been developed for different uses, such as frame memories and line memories dedicated to image processing. Dual port memory is one of them. FIG. 3 shows a block diagram of a conventional dual port memory. Memory IC is 1&
[It is common for I10 buffers to have only 3 column decoders and row decoders, but dual port memory has ■10 buffers (42) (48) and column decoders (
43) (47), and two sets of row decoders (44) and (46) each, so that data can be read and written to any address of one memory array (45) independently from either side. . Furthermore, (40) (50
) is a negative logic NAND gate for giving a write signal according to the chip select, and the same < (41)
(49) is a negative logic NAND gate that provides a read signal in accordance with the chip select signal. This dual
Port memory has begun to be widely used as a communication buffer memory between two or more devices, such as for exchanging data between two CPUs.

However, traditional dual-port memory
Since it is possible to write to the same memory cell equally from two ports, for example, if this memory is used for communication between two CPUs, data managed only by one CPU may be accidentally rewritten by the other CPU. There was a problem.

The present invention has been made in view of the above, and an object of the present invention is to provide a novel dual-port memory that prevents erroneous writing from other ports by simply adding a simple circuit. do.

In order to achieve the above object, the present invention provides a dual port memory that shares one memory cell and has two mutually independent address and data input/output ports.
At least one port is provided with a write control circuit that can set an area in which writing by the other port is prohibited.

Operation-■ With such a configuration, it is possible to prevent data managed by one port from being erroneously rewritten by a rewrite signal from another port.

EMBODIMENT OF THE INVENTION Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 1, (1) and (8) are write control circuits which are characteristic parts of this embodiment, and are circuits that prohibit writing to the area where the memory cell (7) is formed. The area can be arbitrarily designated by an external device such as a CPU. As a specific example of the write control circuit, the memory area is 8.
FIG. 2 shows a circuit that can equally divide the area and control writing in any area. In Figure 2, (21) is a launch circuit that stores write control data (D, ~D?) from an external device, and (22) is a launch circuit that stores the write control data (D, ~D?) from an external device, and (22) divides the address input into memory into 8 equal parts using the upper 3 bits. This is an address decoder that generates a signal to select which memory area is selected. Write control data (D, to D,) to the memory is written to the latch circuit (21) from the external device 1, for example, the CPU. When the command signal is at high level and the enable signal Wπ is at low level, a clock is input to the latch circuit (21) through the AND gate (20) and data is written.

As described above, in this embodiment, data is written when the command signal is at a high level and Wπ is at a low level, but it is also possible to write data when the command signal is at a low level and Wπ is at a high level. - Once a write-protected area is set in the memory, that state is maintained until it is set again. (23) to (30), a gate (31) which receives the output of the latch circuit (21) and the output of the address decoder (22) and performs a negative logic AND, is a write control signal W; This is a negative logic OR gate that outputs □. In this embodiment, writing is prohibited when the write control data is at a high level. In other words, the write control data (D, ~D,) is 10000000. (-8
01), writing is prohibited only in the uppermost area of the memory area divided into eight equal parts. That is, when writing to the uppermost memory area is designated, this control circuit does not output a write signal (WE) to the memory cell. Of course, it is also possible to inhibit writing when the write control data is at a low level, and it goes without saying that in this case the write control data becomes 01111111m (7F,).

Write control to memory is performed for each port on the other side. For example, in FIG. 1, the output of the write control circuit (1) on the left side port is applied to the negative logic NAND gate (9) on the right side port. This NAND gate (9) is also given a separate chip select signal of 3π. The output WE of the NAND gate (9) permits writing when it is at a high level, and inhibits writing when it is at a low level.

(10) is a negative logic NAND gate for reading.

On the other hand, the output of the write control circuit (8) of the right side port is the negative logic NAND gate (8) for writing of the left side port.
2) is applied. (3) is negative logic NAN for reading
This is the D gate. In Figure 1, a memory array (cell) (7) is shared, and I10 buffers (4) (11) and column decoders (5) (
12) Row decoders (6) and (13) are provided as in the conventional case.

In the above embodiment, a write control circuit is provided in both ports so that writing can be inhibited from each other, but this is an unbalanced type in which a write control circuit is provided in only one of the ports and prohibition control can be performed from only one port. It may be configured as follows.

Effects of the Invention According to the present invention, two mutually independent address buses,
A write control circuit is added to at least one port of a dual port memory with a data bus that can set an area where writing is prohibited for the other port.
At least data managed only by one port will not be accidentally rewritten from the other port, making it possible to build a more stable system. Moreover, it can be realized with a simple configuration.

4. Brief Description of the Drawings FIG. 1 is a block diagram of a dual port memory embodying the present invention, and FIG. 2 is a configuration diagram of its main parts.

FIG. 3 is a block diagram of a conventional dual port memory.

(1) (8)-1 write control circuit.

...-Memory array (memory cell).

Claims (1)

[Claims] (1) In a dual port memory that shares one memory cell and has two mutually independent address and data input/output ports, it is possible to set an area in at least one port that prohibits writing by the other port. A dual-port device featuring a write control circuit.
memory.