JPH01123342A - Writing protecting circuit for memory - Google Patents

Abstract

PURPOSE:To prevent the large-scale destruction of a memory area by making a data writing to a memory chip possible only once after a writing permitting signal is outputted. CONSTITUTION:At a time t4, a flip flop 8 is reset with the fall of a writing pulse signal MWR, the flip flop 8 outputs a Q signal of a low level '0', and after that, since a 2-input AND gate 9 makes the writing pulse signal MWR into a prohibited state (inhibits) even if the data writing is executed at a time t5, data cannot be written in a memory chip 1. Namely, the data writing to the memory chip 1 becomes possible only once immediately after a CPU outputs a writing permitting signal IOWR, and the data writing to the memory chip 1 becomes a writing prohibited state, namely, a data protecting state, in any other case. Thus, when the runaway of a program occurs, the destruction of the data stored in an area to be protected can be minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory write protection circuit in an electronic computer system.

(Prior Art) When trying to protect data stored in memory from being destroyed by a runaway program, it has conventionally been necessary to write data to the memory or part of the memory where the data to be protected is stored. A means was provided to enable and prohibit writing. Such means have mainly been configured with hardware or have been realized with software. By this means, data can no longer be written into the memory once it is set to a "prohibited" state until it is then set to a "permitted" state. Conversely, data can be written to a memory that has been set to a "permitted" state until it is next set to a "prohibited" state.

Such memory protection is applied, for example, to random access memory (memory in which data can be read and written at random) used in a control microcomputer of an unmanned commodity trading system. The contents of this memory are used as an electronic journal.

(Problem to be Solved by the Invention) However, conventional memory write protection circuits can prevent data from being destroyed due to program runaway in a write-protected state; There is a problem in that when a runaway occurs, it is impossible to prevent data from being destroyed.

The present invention has been made to solve the above problems,
It is an object of the present invention to provide a memory write protection circuit that can minimize destruction of data stored in an area to be protected when a runaway program occurs.

(Means for solving the problem) A write protection circuit for a memory according to the present invention includes a write permission signal output means for outputting a write permission signal, and a write permission signal output from the write permission signal output means. After that, when a write pulse signal that permits data writing and a write address to which the data should be written are output together with the data to be written, data can be written only once in the area indicated by the write address of the memory. and write control means.

(Function) The write protection circuit of the memory having the above configuration generates a write pulse signal for permitting data writing and a write address to which the data should be written after the write enable signal is output from the write enable signal output means. In addition, when data to be written is input to the memory, the data is written to the memory only once.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an embodiment of a memory write protection circuit according to the present invention. In FIG. 1, memory chip 1
is part of the memory of this circuit, and addresses are assigned in units of 8 bits, making up a total of 84,000 bits.
t, that is, has an address space of 8 Kbytes. This memory chip 1 is 84K bytes (85538b
(not shown)
It is under the control of EOOO (hereinafter Eoo
expressed as oHHX)~P, F F F H
The address of Ex is assigned.

In addition, the memory chip 1 receives a chip select signal of high level "1" at the chip select terminal C8, a read pulse signal of high level rlJ at the successive command terminal RD, and A to A12.
When a 13-bit address is input, 8-bit data is read from the data input/output terminal D-Dr.

Also, memory chip 1 has write permission signal 10WI? After that, a chip select signal of high level "1" is input to the chip select terminal C8, a write pulse signal MWR of high level "1" and an address of 13 bits from Ao to A12 are input to the write command terminal WR. Then, the data input/output terminal is activated only - times. -The data input to D7 is written.

Furthermore, the upper 3 bits of addresses from A13 to A15 are inputted to the chip select terminal C8 via a triple AND gate 5, and all addresses from A to "15" are set to high level "1". , that is, addresses E000 to r' assigned to memory chip 1
When the address of any one EX of P P P and IEx is entered manually, a chip select signal of high level "1" is input.

The bidirectional path buffer 2 is configured such that the data transmission direction can be switched by the read pulse signal MRD.
A high level "1" read pulse signal MRD causes a low level "0" read pulse Ml? from the input/output port 3 to the data bus 4? The direction of data transmission is switched from the data bus 4 to the input/output port 3 by the D signal.

The address decoder 6 selects the addresses E000 to FFFFI (of EX, which are assigned to the memory chip 1).
EX When any address is input, high level "1"
The decoded signal is output to the two-man NAND gate 7. 2
The human powered NAND gate 7 has a decode signal and a write permission signal 10
WI? When the decode signal and write permission signal 10WR are both high level "1",
A preset signal of low level "0" is output to the preset terminal PR of the flip-flop 8. The flip-flop 8 is preset by inputting a low level "0" preset signal, and outputs a high level "1" Q signal from the Q output terminal to the two-manual AND gate 9.

2 manual AND gate 9 is Q signal and write pulse signal MWR
It takes the AND with Q signal and write pulse signal M
When both νR are at high level rlJ, write pulse signal MWI? is input to the write command terminal WR to enable writing of data to the memory chip 1. Note that the flip-flop 8 is reset by the fall of the write pulse signal MWR, and outputs a Q signal of low level "0" from the Q output terminal.

Therefore, even if data can be written to the memory chip 1 by outputting the write permission signal 10WR, the write pulse signal MVI? After outputting and writing data to the memory chip 1, it becomes impossible to write data to the memory chip 1.

Next, the operation of the memory write protection circuit according to the present invention will be explained. First, the operation when the CPU reads data from the memory chip 1 will be described.

When the CPU reads data from memory chip 1,
The read pulse MRD of high level "1" is output, and the address (E
OOO,, Ex-FPFPHEx (predetermined address) is output.

By outputting the read pulse signal MRD and outputting the address, the data stored in the address designated by addresses A to A12 is output to the input/output port. Read pulse signal MI? By the output of D, the bidirectional path buffer 2 is selected so that data is transmitted from the input/output boat 3 to the data bus 4, so the data output to the input/output boat 3 is transferred via the bidirectional path buffer 2. It is output to data bus 4. Therefore, there are no restrictions when the CPU reads data from this memory chip 1.

Next, the operation when the CPU writes data to the memory chip 1 will be explained with reference to the timing chart of FIG.

At time t1, the flip-flop 8 is in a reset state since the write permission signal 10WR is not output (see FIG. 2(g)). Therefore, flip-flop 8
outputs a Q signal of low level rOJ (Fig. 2(f)
reference). Therefore, the CPU outputs the address (see FIG. 2(a)), data (see FIG. 2(b)) as well as the write pulse signal MWD of high level "1" (see FIG. 2(d)). Even if the chip select signal of level "1" is output (see FIG. 2 (C)), the write pulse signal MWR is not input to the write command terminal VR of the memory chip 1 by the two-manual AND gate 9. (see Figure 2(e)),
No data is written to memory chip 1.

Note that the flip-flop 8 is reset by a power-on signal POW ON or a reset signal N inputted to a reset terminal R by power-on or a reset switch (not shown).

Next, at time t2, the CPU outputs a write permission signal 10WR of high level "1" (see FIG. 2(g)).
From EOOO to PPPPHEx, the address decoder 6 becomes high level “1” due to the output of the predetermined address EX.
Since the flip-flop 8 outputs a decoded signal of "1", the flip-flop 8 outputs a high level "1" reset signal to the preset terminal PI? and outputs a Q signal of high level "1" (see FIG. 2(f)).

Therefore, write command terminal Ml? of memory chip 1? It becomes possible to input the write pulse signal MWR to the .

At time t3, the CPU outputs the iF included pulse MWD signal of high level "1" (see FIG. 2(d)) and the address (EOOO).
~ FFFFIIEX (see Figure 2 (a)) and chip select signal (see Figure 2 (C)), and output data (see Figure 2 (b)). The write pulse signal MVR is inputted to the write command terminal WR of the memory chip 1 (see FIG. 2(e)), and writing of data to the memory chip 1 is executed.

At time t4, the flip-flop 8 receives the write pulse signal MW.
It is reset by the fall of R and outputs a Q signal of low level "0" (see Figure 2 (r)), and thereafter at time t.
Even if data is written to the memory chip 5, the two-manual AND gate 9 inhibits the write pulse signal MWR, making it impossible to write data to the memory chip 1. That is, the CPU outputs the write permission signal 10WR.
It is possible to write data to the memory chip 1 only once immediately after outputting , and at other times, the writing is prohibited, that is, the data is protected.

(Effects of the Invention) As explained above, according to the present invention, data can be written to the memory chip only once after the write permission signal is output, and when the write permission signal is not output. Of course, even if the CPU (program) goes out of control, the data stored in the memory chip is protected, and the CPU (program) goes out of control immediately after outputting the write permission signal. However, at worst the data that is destroyed is 1 word (= 1 byte - 8 bits)
), thereby providing a memory write protection circuit that can prevent large-scale destruction of the memory area.

Therefore, compared to conventional memory write protection circuits, it is possible to expect an improvement in the protection effect for large amounts of data.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
3 is a timing chart showing the operation of the circuit shown in the figure. 1...Memory, 2...Bidirectional path buffer, 3...
・I/O boat, 4...Data bus, 5...3 manual AND gate, 6...Address decoder, 7...2
Human powered NAND gate, 8...Flip-flop, 9...
・Two-person power and gate.

Claims (1)

[Claims] By inputting the data to be written into the memory together with a write pulse signal that permits writing of data and a write address to which the data is to be written, the memory is configured to write the data into the area indicated by the address. In the write protection circuit, write permission signal output means outputs a write permission signal, and after the write permission signal is output, the write pulse signal and the write address are output to the memory. A write protection circuit for a memory, comprising: a write control means that allows data to be written only once; and a write protection circuit for a memory.