JPH0575845U - CPU interrupt table data fixed circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a CPU interrupt table data fixing circuit capable of protecting table data written in a RAM during runaway. [Configuration] 1 is a CPU, which outputs a response signal to a logic circuit 2 in response to an external interrupt request. 8-bit data called a vector is output from the logic circuit 2 to the CPU 1. This determines the table address. The data of this address is placed on the RAM 3 but is output from the logic circuit 2.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an output circuit of table data indicating a start address of an interrupt processing program fetched by a CPU when a CPU interrupts, and particularly to setting table data by a logic circuit.

[0002]

[Prior Art]

 In the conventional 16-bit CPU and the like, the head address (table data) of the interrupt processing program is supplied from the external memory on the memory map of the CPU during interrupt processing. This external memory normally uses RAM.

[0003]

[Problems to be solved by the device]

 Since the conventional table data is written in the RAM, it may be rewritten when a runaway occurs due to a bug in the program or incompleteness during program development.

Therefore, an object of the present invention is to provide a CPU interrupt table data fixing circuit capable of protecting table data in case of runaway.

[0005]

[Means for Solving the Problems]

 Therefore, in order to achieve the above-mentioned object, the present invention is provided with a logic circuit section which allows the table data on the memory map of the CPU to be written only once.

[0006]

[Action]

 According to the present invention, when a program goes out of control, it is possible to reliably perform the operation by externally issuing an interrupt request by an external operation.

The recovery described here means that the program can be restarted from various addresses on the program indicated by the table data. (In a word processor, etc., you may want to restart a program that clears the document when the power is turned on by the program, with the document protected during a runaway.)

[0008]

【Example】

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the present invention and an operation sequence. FIG. 2 is a block diagram showing an outline of the contents of the logic section shown in FIG. FIG. 3 shows an example of the circuit of the logic section shown in FIG. 2, which can be written only once.

In FIG. 1, a response signal is output from the CPU 1 to the logic circuit 2 in response to an external interrupt request, and 8-bit data called a vector is output to the CPU 1. Although the table address is determined by this, although the data of this address is normally placed in the RAM 3, FIG. 1 shows that it is output from the logic unit 2.

In FIG. 2, the table data output from the CPU 1 is divided by the address decoder 2a into a table data read (A), a write (B), and a RAM 3 chip select signal (C). When there is a RAM area on the table address, RAM chip select must be inactive when selecting table data. When the CPU 1 reads the table data, it is output from 3state. The output data is stored in the logic unit 2b (D) and is written by the CPU at the time of initial setting.

FIG. 3 is a circuit example of the logic unit 2b (D), in which the data at the time of initialization is latched by the flip-flop, and the data is written once by the output of the flip-flop at the bottom of each block of (I) to (IV). After that, the circuit cannot be written until reset is entered. Since the CPU is a 16-bit bus, the table data 4 Bytes are divided into two and are output in a time-division manner from the combinational circuit of (A) to (P) of FIG.

[0013]

[Effect of the device]

 As described above, according to the present invention, the table data becomes fixed once it is written in the logic circuit section by the program. Since it does not change when it is taken, it can be reliably restored.

[Brief description of drawings]

FIG. 1 is a block diagram and an operation sequence showing a configuration of an embodiment of a CPU interrupt table fixing circuit of the present invention.

FIG. 2 is a block diagram showing an outline of contents of a logic unit shown in FIG.

3 is a circuit example of a once-writable logic unit shown in FIG. 2;

[Explanation of symbols]

 1 CPU 2 Logic circuit 3 RAM

Claims (1)

[Scope of utility model registration request] 1. A CPU comprising a CPU and an interrupt processing start address output circuit of the CPU, and provided with a logic circuit capable of writing the interrupt processing start address on the memory access of the CPU only once. Interrupt table data fixed circuit.