JPS6399948U - - Google Patents
Info
- Publication number
- JPS6399948U JPS6399948U JP1986195449U JP19544986U JPS6399948U JP S6399948 U JPS6399948 U JP S6399948U JP 1986195449 U JP1986195449 U JP 1986195449U JP 19544986 U JP19544986 U JP 19544986U JP S6399948 U JPS6399948 U JP S6399948U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- flip
- signal
- flop circuit
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000013256 coordination polymer Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Storage Device Security (AREA)
Description
第１図はこの考案の一実施例を示すメモリプロ
テクト回路の回路図、第２図は上記メモリプロテ
クト回路の動作タイムチヤート図である。
図中、１はアンド回路（第１の論理回路）、２
はＤ形フリツプフロツプ回路、３はＯＲの負論理
のナンド回路（第２の論理回路）である。
FIG. 1 is a circuit diagram of a memory protect circuit showing an embodiment of this invention, and FIG. 2 is an operation time chart of the memory protect circuit. In the figure, 1 is an AND circuit (first logic circuit), 2
3 is a D-type flip-flop circuit, and 3 is an OR negative logic NAND circuit (second logic circuit).
Claims (1)
アドレス信号のうち所定アドレスで信号を出力す
る第１の論理回路と、該所定アドレスにおける命
令コードフエツチサイクルで出力される前記ＣＰ
Ｕの動作制御信号でセツト、リセツトされるフリ
ツプフロツプ回路と、該フリツプフロツプ回路の
セツト側の出力信号とメモリの書き込み信号とが
入力される第２の論理回路とを備え、 前記フリツプフロツプ回路がセツトされたとき
のみ前記書き込み信号を出力するようにしたこと
を特徴とするメモリプロテクト回路。 (2) 実用新案登録請求の範囲(1)において、前記
第１の論理回路はアンド回路であり、前記フリツ
プフロツプ回路であり、第２の論理回路はナンド
回路であることを特徴とするメモリプロテクト回
路。 (3) 実用新案登録請求の範囲(1)および(2)にお
いて、前記フリツプフロツプ回路は、前記所定ア
ドレスの書き込み命令の実行の際にセツトされ、
リターン命令の実行の際にリセツトされるように
したことを特徴とするメモリプロテクト回路。[Claims for Utility Model Registration] (1) A first logic circuit that receives an address signal from a CPU and outputs a signal at a predetermined address of the address signal, and outputs a signal at an instruction code fetch cycle at the predetermined address. The CP to be
The flip-flop circuit includes a flip-flop circuit that is set and reset by the operation control signal of U, and a second logic circuit to which the output signal on the set side of the flip-flop circuit and the write signal of the memory are input, and the flip-flop circuit is set. A memory protection circuit characterized in that the write signal is output only when the write signal is output. (2) The memory protection circuit according to claim (1), wherein the first logic circuit is an AND circuit, the flip-flop circuit is the flip-flop circuit, and the second logic circuit is a NAND circuit. . (3) In claims (1) and (2) of the utility model registration, the flip-flop circuit is set upon execution of a write instruction for the predetermined address;
A memory protection circuit characterized in that it is reset when a return instruction is executed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986195449U JPH0325230Y2 (en) | 1986-12-19 | 1986-12-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986195449U JPH0325230Y2 (en) | 1986-12-19 | 1986-12-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6399948U true JPS6399948U (en) | 1988-06-29 |
| JPH0325230Y2 JPH0325230Y2 (en) | 1991-05-31 |
Family
ID=31153345
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986195449U Expired JPH0325230Y2 (en) | 1986-12-19 | 1986-12-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0325230Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0335386A (en) * | 1989-06-30 | 1991-02-15 | Toshiba Corp | Portable electronic device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60239850A (en) * | 1984-05-14 | 1985-11-28 | Fuji Xerox Co Ltd | Microprocessor system provided with no-break memory |
-
1986
- 1986-12-19 JP JP1986195449U patent/JPH0325230Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60239850A (en) * | 1984-05-14 | 1985-11-28 | Fuji Xerox Co Ltd | Microprocessor system provided with no-break memory |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0335386A (en) * | 1989-06-30 | 1991-02-15 | Toshiba Corp | Portable electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0325230Y2 (en) | 1991-05-31 |
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