JPS6356449U - - Google Patents
Info
- Publication number
- JPS6356449U JPS6356449U JP14731486U JP14731486U JPS6356449U JP S6356449 U JPS6356449 U JP S6356449U JP 14731486 U JP14731486 U JP 14731486U JP 14731486 U JP14731486 U JP 14731486U JP S6356449 U JPS6356449 U JP S6356449U
- Authority
- JP
- Japan
- Prior art keywords
- stack
- memory
- holds
- electronic computer
- abnormality
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 5
- 230000005856 abnormality Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Executing Machine-Instructions (AREA)
Description
第１図はこの考案の一実施例を示す電子計算機
のポツプ命令機構図、第２図は従来の電子計算機
ポツプ命令機構図、第３図は従来のポツプ命令を
使用する場合のプログラムコード例を示す図でな
り、２１はスタツクアドレスを保持するメモリ、
２２はスタツク最終アドレスを保持するメモリ、
２３は比較回路、２４は割り込み発生信号ライン
である。なお、図中同一符号は同一又は相当部分
を示す。
Fig. 1 is a diagram of the pop instruction mechanism of an electronic computer showing an embodiment of this invention, Fig. 2 is a diagram of the pop instruction mechanism of a conventional computer, and Fig. 3 is an example of program code when using the conventional pop instruction. In the figure, 21 is a memory that holds stack addresses;
22 is a memory that holds the stack final address;
23 is a comparison circuit, and 24 is an interrupt generation signal line. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
に関するスタツクアドレスを保持するメモリと、
スタツク先頭アドレスを保持するメモリと、この
２つのメモリの内容を比較する比較回路と、比較
の結果異常の場合、スタツク異常割り込みを発生
させる機構とを備えたことを特徴とする電子計算
機。 a memory that holds stack addresses related to pop-up instructions belonging to machine instructions of an electronic computer;
An electronic computer comprising: a memory that holds a stack top address; a comparison circuit that compares the contents of the two memories; and a mechanism that generates a stack abnormality interrupt when the comparison results in an abnormality.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14731486U JPS6356449U (en) | 1986-09-26 | 1986-09-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14731486U JPS6356449U (en) | 1986-09-26 | 1986-09-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6356449U true JPS6356449U (en) | 1988-04-15 |
Family
ID=31060561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14731486U Pending JPS6356449U (en) | 1986-09-26 | 1986-09-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6356449U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007042131A (en) * | 1995-10-06 | 2007-02-15 | Patriot Scientific Corp | Structure of reduced instruction set computer type microprocessor |
-
1986
- 1986-09-26 JP JP14731486U patent/JPS6356449U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007042131A (en) * | 1995-10-06 | 2007-02-15 | Patriot Scientific Corp | Structure of reduced instruction set computer type microprocessor |
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