JPH0255341U - - Google Patents
Info
- Publication number
- JPH0255341U JPH0255341U JP13152288U JP13152288U JPH0255341U JP H0255341 U JPH0255341 U JP H0255341U JP 13152288 U JP13152288 U JP 13152288U JP 13152288 U JP13152288 U JP 13152288U JP H0255341 U JPH0255341 U JP H0255341U
- Authority
- JP
- Japan
- Prior art keywords
- decoder
- input
- output device
- address
- access data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案実施例の構成を示すブロツク図
、第２図は従来例の構成を示すブロツク図である
。
１…ＭＰＵ、２…デコーダ、３…アドレスバス
、４…データバス、５…ＲＡＭ、６…ＲＡＭ／デ
コーダ切換回路、１０…入出力装置。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional example. 1...MPU, 2...Decoder, 3...Address bus, 4...Data bus, 5...RAM, 6...RAM/decoder switching circuit, 10...I/O device.
Claims (1)
アドレスコードを発生するデコーダと、マイクロ
プロセツサからのアドレスデータとデコーダアク
セスデータとの対応関係の情報を書き換え可能に
記憶するメモリーとを備え、上記メモリーの情報
にしたがつてプログラム上のアドレスをデコーダ
アクセスデータに変換してデコーダへ与え、デコ
ーダから入出力装置のアドレスコードを入出力装
置へ与えることを特徴とするマイクロプロセツサ
の入出力デコード回路。 It is equipped with a decoder that generates an address code for an input/output device according to decoder access data, and a memory that rewritably stores information on the correspondence between the address data from the microprocessor and the decoder access data. 1. An input/output decoding circuit for a microprocessor, characterized in that an address on a program is converted into decoder access data and given to the decoder in accordance with the above, and an address code of the input/output device is given to the input/output device from the decoder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13152288U JPH0255341U (en) | 1988-10-07 | 1988-10-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13152288U JPH0255341U (en) | 1988-10-07 | 1988-10-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0255341U true JPH0255341U (en) | 1990-04-20 |
Family
ID=31387671
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13152288U Pending JPH0255341U (en) | 1988-10-07 | 1988-10-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0255341U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6155765A (en) * | 1984-08-27 | 1986-03-20 | Nec Corp | I/o address decoder circuit |
-
1988
- 1988-10-07 JP JP13152288U patent/JPH0255341U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6155765A (en) * | 1984-08-27 | 1986-03-20 | Nec Corp | I/o address decoder circuit |
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