JPS63179547U - - Google Patents
Info
- Publication number
- JPS63179547U JPS63179547U JP7187387U JP7187387U JPS63179547U JP S63179547 U JPS63179547 U JP S63179547U JP 7187387 U JP7187387 U JP 7187387U JP 7187387 U JP7187387 U JP 7187387U JP S63179547 U JPS63179547 U JP S63179547U
- Authority
- JP
- Japan
- Prior art keywords
- accessed
- state
- address
- microprocessor
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004044 response Effects 0.000 claims description 6
- 238000007726 management method Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Description
第１図は本考案の一実施例の構成図、第２図は
従来例の構成図である。
１…マイクロプロセツサ、２…メモリ、４…ゲ
ート回路、５…応答信号発生回路、９…ラツチ回
路、１０…比較回路。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional example. DESCRIPTION OF SYMBOLS 1...Microprocessor, 2...Memory, 4...Gate circuit, 5...Response signal generation circuit, 9...Latch circuit, 10...Comparison circuit.
Claims (1)
するマイクロプロセツサのメモリ管理方式であつ
て、 ユーザ状態でアクセスできるユーザ領域と特権
状態でのみアクセスできる特権領域との境界のア
ドレスが設定されるラツチ回路と、 前記ラツチ回路に設定された境界のアドレスお
よびアクセスされるメモリのアドレスが与えられ
、両アドレスを比較する比較回路と、 ユーザ状態であるか特権状態であるかを示す状
態信号が前記マイクロプロセツサから与えられる
とともに、前記比較回路の出力が与えられるゲー
ト回路と、 前記ゲート回路の出力に基づいて、ユーザ状態
で、かつ、前記アクセスされるメモリのアドレス
がユーザ状態ではアクセスできない前記特権領域
のアドレスであるときには、アクセスに応答する
応答信号を発生せず、正常にアクセスされるとき
には、アクセスに応答する応答信号を発生して前
記マイクロプロセツサに与える応答信号発生回路
とを備えることを特徴とするマイクロプロセツサ
のメモリ管理方式。[Claims for Utility Model Registration] A memory management system for a microprocessor that has two operating states, a user state and a privileged state, which includes a user area that can be accessed in the user state and a privileged area that can only be accessed in the privileged state. A latch circuit to which a boundary address is set; a comparison circuit to which the latch circuit is given the boundary address set and the memory address to be accessed and compares both addresses; a gate circuit to which the microprocessor supplies a state signal indicating whether the memory is in the user state and the address of the memory to be accessed is determined based on the output of the gate circuit; When the address is in the privileged area that cannot be accessed in the user state, a response signal in response to the access is not generated, and when the access is normally performed, a response signal in response to the access is generated and the response signal is given to the microprocessor. A memory management method for a microprocessor, characterized by comprising a generator circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7187387U JPS63179547U (en) | 1987-05-14 | 1987-05-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7187387U JPS63179547U (en) | 1987-05-14 | 1987-05-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63179547U true JPS63179547U (en) | 1988-11-21 |
Family
ID=30914822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7187387U Pending JPS63179547U (en) | 1987-05-14 | 1987-05-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63179547U (en) |
-
1987
- 1987-05-14 JP JP7187387U patent/JPS63179547U/ja active Pending
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