JPS61128748U - - Google Patents
Info
- Publication number
- JPS61128748U JPS61128748U JP1192985U JP1192985U JPS61128748U JP S61128748 U JPS61128748 U JP S61128748U JP 1192985 U JP1192985 U JP 1192985U JP 1192985 U JP1192985 U JP 1192985U JP S61128748 U JPS61128748 U JP S61128748U
- Authority
- JP
- Japan
- Prior art keywords
- memory access
- address
- bus
- line switching
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 9
- MHABMANUFPZXEB-UHFFFAOYSA-N O-demethyl-aloesaponarin I Natural products O=C1C2=CC=CC(O)=C2C(=O)C2=C1C=C(O)C(C(O)=O)=C2C MHABMANUFPZXEB-UHFFFAOYSA-N 0.000 description 3
- 230000000737 periodic effect Effects 0.000 description 1
Landscapes
- Bus Control (AREA)
Description
第１図は、本考案の実施例によるメモリアクセ
ス制御回路のブロツク図、第２図は、本考案の実
施例によるメモリアクセス制御回路のアドレス線
入替え回路とアドレスバス、アドレス入力を表わ
す図、第３図は、アドレス線入替え回路の切り換
え信号ｓ（信号）の周期図、第４図ａ，ｂ
は、本考案の実施例によるメモリアクセス制御回
路においてＭＰＵがＲＡＭにアクセスした際の図
、第５図ａ，ｂは、本考案の実施例によるメモリ
アクセス制御回路においてＤＭＡＣがＲＡＭにア
クセスした際の図、第６図は、本考案の実施例に
よるメモリアクセス制御回路のビツト情報対応図
、第７図は、従来のメモリアクセス制御回路のブ
ロツク図、第８図ａ，ｂはＭＰＵがＲＡＭをアク
セスする際のデータ、付加情報のバツフアエリア
を表わす図、第９図はａ，ｂはＤＭＡＣがＲＡＭ
をアクセスする際のデータのバツフアエリアを表
わす図、第１０図は、ＤＭＡＣがＲＡＭをアクセ
スする際の通信バスラインの図である。
１……マイクロプロセツサＭＰＵ、２……ダイ
レクトメモリアクセス制御器ＤＭＡＣ、３……ラ
ンダムアクセスメモリＲＡＭ、４……通信ポート
、５……メモリアクセスデバイス検出回路、６…
…アドレス線入替え回路、Ｂ……入出力バス、Ｂ
１……アドレスバス、Ｂ２……データバス、コン
トロールバス。
FIG. 1 is a block diagram of a memory access control circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing an address line switching circuit, an address bus, and an address input of the memory access control circuit according to an embodiment of the present invention. Figure 3 is a periodic diagram of the switching signal s (signal) of the address line switching circuit, Figure 4 a, b
5A and 5B are diagrams when the MPU accesses the RAM in the memory access control circuit according to the embodiment of the present invention, and FIGS. 5a and 5b are diagrams when the DMAC accesses the RAM in the memory access control circuit according to the embodiment of the present invention. 6 is a bit information correspondence diagram of a memory access control circuit according to an embodiment of the present invention, FIG. 7 is a block diagram of a conventional memory access control circuit, and FIG. 8 a and b are diagrams showing how the MPU accesses the RAM. Figure 9 shows the buffer area of data and additional information when
FIG. 10 is a diagram showing the communication bus line when the DMAC accesses the RAM. DESCRIPTION OF SYMBOLS 1... Microprocessor MPU, 2... Direct memory access controller DMAC, 3... Random access memory RAM, 4... Communication port, 5... Memory access device detection circuit, 6...
...Address line switching circuit, B...Input/output bus, B
1 ...address bus, B2 ...data bus, control bus.
Claims (1)
クセス制御器に入出力バスを介してアクセスされ
データ情報が入出力されるメモリと、前記マイク
ロプロセツサと前記ダイレクトメモリアクセス制
御器のどちらが前記メモリアクセスするかの検出
信号をアドレス線切り換え信号としてアドレスバ
スのアドレス線の入替えを行なうアドレス線入替
え回路よりなるメモリアクセス制御回路。 A memory that is accessed by a microprocessor or a direct memory access controller via an input/output bus to input and output data information, and a detection signal indicating whether the microprocessor or the direct memory access controller accesses the memory. A memory access control circuit consisting of an address line switching circuit that switches address lines of an address bus as an address line switching signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1192985U JPS61128748U (en) | 1985-01-30 | 1985-01-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1192985U JPS61128748U (en) | 1985-01-30 | 1985-01-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61128748U true JPS61128748U (en) | 1986-08-12 |
Family
ID=30494510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1192985U Pending JPS61128748U (en) | 1985-01-30 | 1985-01-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61128748U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59135530A (en) * | 1983-01-21 | 1984-08-03 | Fujitsu Kiden Ltd | Memory reading system using dma |
| JPS59189432A (en) * | 1983-04-12 | 1984-10-27 | Fujitsu Kiden Ltd | Memory storing system by direct memory access |
-
1985
- 1985-01-30 JP JP1192985U patent/JPS61128748U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59135530A (en) * | 1983-01-21 | 1984-08-03 | Fujitsu Kiden Ltd | Memory reading system using dma |
| JPS59189432A (en) * | 1983-04-12 | 1984-10-27 | Fujitsu Kiden Ltd | Memory storing system by direct memory access |
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