JPH0474344U - - Google Patents
Info
- Publication number
- JPH0474344U JPH0474344U JP11810690U JP11810690U JPH0474344U JP H0474344 U JPH0474344 U JP H0474344U JP 11810690 U JP11810690 U JP 11810690U JP 11810690 U JP11810690 U JP 11810690U JP H0474344 U JPH0474344 U JP H0474344U
- Authority
- JP
- Japan
- Prior art keywords
- microprocessor
- flag
- power
- power supply
- supply terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000011156 evaluation Methods 0.000 claims description 5
- 238000001514 detection method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図は本考案の実施例による、評価用チツプ
の内部配線図、第２図は従来の評価用チツプの内
部配線図である。
１……評価用チツプ、２……パワーオンフラグ
用電源端子、３……低電圧検出回路、４……低電
圧検出信号線、５……パワーオンフラグ、６……
リードバツフア、７……電源端子、８……電源端
子用低電圧検出回路、９……電源端子用低電圧検
出信号線、１０……内部データ・バス、１１……
マイクロプロセツサ応用システムの電源、１２…
…マイクロプロセツサ評価用システムの電源。
FIG. 1 is an internal wiring diagram of an evaluation chip according to an embodiment of the present invention, and FIG. 2 is an internal wiring diagram of a conventional evaluation chip. 1...Evaluation chip, 2...Power-on flag power supply terminal, 3...Low voltage detection circuit, 4...Low voltage detection signal line, 5...Power-on flag, 6...
Lead buffer, 7...Power supply terminal, 8...Low voltage detection circuit for power supply terminal, 9...Low voltage detection signal line for power supply terminal, 10...Internal data bus, 11...
Power supply for microprocessor application system, 12...
...Power supply for microprocessor evaluation system.
Claims (1)
を検出して結果を保持するフラグ（以下パワーオ
ンフラグと称する）を有するマイクロプロセツサ
を用いたマイクロプロセツサ応用システムの評価
を行なうためにターゲツトとなるマイクロプロセ
ツサのエミユレーシヨンを行ない、動作中のレジ
スタ情報、バンク情報を保持する評価用チツプの
うち、通常の電源用端子とは別に、パワーオンフ
ラグ電源用端子を有することを特徴とする評価用
チツプ。 A target microprocessor is used to evaluate a microprocessor application system that uses a microprocessor that has a flag (hereinafter referred to as a power-on flag) that detects the disconnection or reduction of power applied to the microprocessor and retains the result. An evaluation chip that emulates a processor and holds register information and bank information during operation, and is characterized by having a power-on flag power supply terminal in addition to a normal power supply terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11810690U JPH0474344U (en) | 1990-11-09 | 1990-11-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11810690U JPH0474344U (en) | 1990-11-09 | 1990-11-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0474344U true JPH0474344U (en) | 1992-06-29 |
Family
ID=31866011
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11810690U Pending JPH0474344U (en) | 1990-11-09 | 1990-11-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0474344U (en) |
-
1990
- 1990-11-09 JP JP11810690U patent/JPH0474344U/ja active Pending
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