JPS61603U

JPS61603U - programmable controller

Info

Publication number: JPS61603U
Application number: JP8470084U
Authority: JP
Inventors: 幸男加藤
Original assignee: オムロン株式会社
Priority date: 1984-06-07
Filing date: 1984-06-07
Publication date: 1986-01-06

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例に係るプログラマブルΦコ
ントローラの構成を示すブロック図、第２図は従来のプ
ログラマブル・コント口・−ラノ構成を示すブロック図
である。一１・・・・・・基本ユニット、２・・−拡張１／Ｏ
ユニット、５・・曲ケーブル、１３，２２・・曲電源回
路、１１・・・・・・マイクロコンピュータ、１２，２
２・・・・・・Ｉ／ＯｍＵ御回路、２４・・・・・・イ
ンバータ、２５．２６・・・・・・オープケコレクタゲ
ート。FIG. 1 is a block diagram showing the configuration of a programmable Φ controller according to an embodiment of this invention, and FIG. 2 is a block diagram showing a conventional programmable controller configuration. -1... Basic unit, 2...-Expansion 1 /O
Unit, 5...Song cable, 13,22...Song power supply circuit, 11...Microcomputer, 12,2
2...I/OmU control circuit, 24...Inverter, 25.26...Obke collector gate.

Claims

[Claims for Utility Model Registration] Programmable controller basic unit equipped with a CPU and external I/O, and expansion I/O equipped with external I/O
units are connected to a common bus line via connectors, and the basic unit and expansion I/O
A programmable controller comprising an independent power supply for each unit; the expansion I/O unit is provided with an active LOW power-on detection signal corresponding to a period during which the unit is powered on. The base unit is provided with a power detection circuit that generates an active LOW power-on signal in response to a power-on period of the unit; a power-on detection signal sent from the power supply detection circuit of the expansion I/O unit;
In response to the fall of the logical sum with the power-on detection signal obtained from the power supply detection circuit of the basic unit, the active L
a reset circuit that generates a reset signal consisting of an OW one-shot pulse; the internal circuit of the basic unit is reset by the one-shot pulse, and the internal circuit of the expansion I/O unit is configured to perform a predetermined reset process; The reset processing is performed by a one-shot pulse sent from the basic unit via the signal line of the expansion I/O unit; , and only during a period in which power-off of the basic unit is detected via a predetermined signal line,
an auxiliary reset circuit that generates an active LOW auxiliary reset signal; an OR circuit that obtains a logical sum of the auxiliary reset signal and the reset signal sent from the basic unit via a predetermined signal line; A programmable controller characterized in that the internal circuit of the expansion I/O unit is reset by the output of the OR circuit.