JPS6010349U - memory sharing device - Google Patents
memory sharing deviceInfo
- Publication number
- JPS6010349U JPS6010349U JP9899883U JP9899883U JPS6010349U JP S6010349 U JPS6010349 U JP S6010349U JP 9899883 U JP9899883 U JP 9899883U JP 9899883 U JP9899883 U JP 9899883U JP S6010349 U JPS6010349 U JP S6010349U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- microprocessor
- microprocessors
- slave
- sharing device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Multi Processors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例を示すブロック構成図、第２
図は第１図におけるマイクロプロセッサ１．２間の結合
回路の一実施例を示す回路図、第３図は第２図における
リクエスト信号と確認応答信号の関係を示すタイムチャ
ートである。
１．２・・・・・・マイクロプロセッサ、３・・・・・
・ランダムアクセスメモリ、４１，４□、 ５．、
５□、７□。
７□・・・・・・バッファ、８，９・・・・・・Ｄ型フ
リップフロップ。Fig. 1 is a block diagram showing one embodiment of the present invention;
This figure is a circuit diagram showing an embodiment of the coupling circuit between the microprocessors 1 and 2 in FIG. 1, and FIG. 3 is a time chart showing the relationship between the request signal and the acknowledgment signal in FIG. 2. 1.2...Microprocessor, 3...
・Random access memory, 41,4□, 5. ,
5□, 7□. 7□...Buffer, 8,9...D type flip-flop.
Claims (1)
共有して使用するにおいて、上記メモリと２台のマイク
ロプロセッサ間はデータバス、アドレスバス及ヒ読出シ
、書込みコントロールバスにおいて夫々バッファを介在
して結合し、上記２台のマイクロプロセッサのうち一方
をマスク側、他方をスレーブ側にしてスレーブ側マイク
ロプロセッサからマスク側マイクロプロセッサへのメモ
リ使用リクエスト信号を与えかつこのリクエスト信号に
対するマスク側マイクロプロセッサからの確認応答信号
をスレーブ側マイクロプロセッサに与えると共に該プロ
セッサとメモリとの間を結合するよう当該バッファを動
作可能にする結合回路を設けたことを特徴とするメモリ
共有装置。When the random access memory is shared and used by two microprocessors, the memory and the two microprocessors are coupled via buffers in a data bus, an address bus, and a read/write control bus, respectively; One of the two microprocessors mentioned above is set as the mask side and the other as the slave side, and the slave side microprocessor gives a memory use request signal to the mask side microprocessor, and the acknowledgment signal from the mask side microprocessor in response to this request signal. 1. A memory sharing device comprising: a coupling circuit for providing a slave microprocessor with a buffer and enabling said buffer to operate to couple between said processor and said memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9899883U JPS6010349U (en) | 1983-06-27 | 1983-06-27 | memory sharing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9899883U JPS6010349U (en) | 1983-06-27 | 1983-06-27 | memory sharing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6010349U true JPS6010349U (en) | 1985-01-24 |
Family
ID=30234795
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9899883U Pending JPS6010349U (en) | 1983-06-27 | 1983-06-27 | memory sharing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6010349U (en) |
-
1983
- 1983-06-27 JP JP9899883U patent/JPS6010349U/en active Pending
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