JPS58164028U - Input/output data buffer device - Google Patents
Input/output data buffer deviceInfo
- Publication number
- JPS58164028U JPS58164028U JP6127882U JP6127882U JPS58164028U JP S58164028 U JPS58164028 U JP S58164028U JP 6127882 U JP6127882 U JP 6127882U JP 6127882 U JP6127882 U JP 6127882U JP S58164028 U JPS58164028 U JP S58164028U
- Authority
- JP
- Japan
- Prior art keywords
- data buffer
- input
- buffer device
- data
- output data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は入出力データ・バッファ装置の位置を示すブロ
ック図、第２図は入出力データ・バッファ装置内のデー
タ転送回路の構成を示すブロック図、第３図はチャネル
・ユニットからのデータ転送要求受付回路と一時データ
バツファ内のデータが未格納であることを示すフリップ
フロップの制御回路図、第４図は一時データバツファが
使用可能となるデータ位置図、第５図は一時データバッ
ファの使用可能ミ不可能を示すフリップフロップの制御
回路図、第６図はデータ・バッファ・ストレージ書込み
動作の概略図、第７図はデータ・バッファ・ストレージ
の書込み信号制御回路図、第′８図はデータ・バッファ
・ストレージの書込みデータ選択回路図、第９図はデー
タ・バッファ・ストレージの読出しデータからチャネル
・ユニットへの転送データを選択する選択回路図、第１
０図は一時データバツファの入力選択回路図、第１１図
はチャネル・ユニットへの転送データのデータ選択回路
図である。
１０・・・チャネル・ユニット、１４・・・入出力バッ
ファ・ユニット、１８・・・主記憶ユニット、２０・・
・データ拳バッファ・ストレージ、２１・・・一時デー
タ・バッファ、２２・・・書込みデータ選択回路、２３
・・・一時データ・バッファ入力選択回路、２４・・・
出力データ選択回路、２５・・・転送データ選択回路、
２６・・・出力データ選択回路。Figure 1 is a block diagram showing the location of the input/output data buffer device, Figure 2 is a block diagram showing the configuration of the data transfer circuit within the input/output data buffer device, and Figure 3 is the data transfer from the channel unit. A control circuit diagram of the request reception circuit and a flip-flop indicating that data in the temporary data buffer is not stored. Figure 4 is a data position diagram where the temporary data buffer can be used. Figure 5 is a diagram of the temporary data buffer. FIG. 6 is a schematic diagram of the data buffer storage write operation; FIG. 7 is a write signal control circuit diagram of the data buffer storage; FIG. is a write data selection circuit diagram of the data buffer storage, and FIG. 9 is a selection circuit diagram for selecting transfer data to the channel unit from read data of the data buffer storage.
0 is an input selection circuit diagram of a temporary data buffer, and FIG. 11 is a data selection circuit diagram of transfer data to a channel unit. 10... Channel unit, 14... Input/output buffer unit, 18... Main memory unit, 20...
- Data fist buffer storage, 21... Temporary data buffer, 22... Write data selection circuit, 23
...Temporary data buffer input selection circuit, 24...
Output data selection circuit, 25...transfer data selection circuit,
26...Output data selection circuit.
Claims (1)
から時分割的にアクセスされるチャネイレデータバツフ
ァ装置において、該データ・バッファ装置の前段！ビ設
けられ書込データを一時的に記憶しておく記憶手段と、
該データーバッファの後段に設けられ読出しデータを一
時的に記憶しておく記憶手段と、これら面記憶手段の有
効、無効を表わす表示手段と、該表示手段の値により上
記データ・バッファ装置の部分書込みを制御する手段と
から成ることを特徴とする入出力データ・バッファ装置
。In a channel data buffer device provided between an input/output device and a main memory device and accessed by the same device in a time-sharing manner, the preceding stage of the data buffer device! storage means for temporarily storing written data;
A storage means provided after the data buffer for temporarily storing read data, a display means for indicating whether these storage means are valid or invalid, and a partial write of the data buffer device based on the value of the display means. An input/output data buffer device comprising: means for controlling.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6127882U JPS58164028U (en) | 1982-04-28 | 1982-04-28 | Input/output data buffer device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6127882U JPS58164028U (en) | 1982-04-28 | 1982-04-28 | Input/output data buffer device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58164028U true JPS58164028U (en) | 1983-11-01 |
Family
ID=30071484
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6127882U Pending JPS58164028U (en) | 1982-04-28 | 1982-04-28 | Input/output data buffer device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58164028U (en) |
-
1982
- 1982-04-28 JP JP6127882U patent/JPS58164028U/en active Pending
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