JPS59130146U - memory device - Google Patents

memory device

Info

Publication number
JPS59130146U
JPS59130146U JP1951083U JP1951083U JPS59130146U JP S59130146 U JPS59130146 U JP S59130146U JP 1951083 U JP1951083 U JP 1951083U JP 1951083 U JP1951083 U JP 1951083U JP S59130146 U JPS59130146 U JP S59130146U
Authority
JP
Japan
Prior art keywords
memory
memory device
storing
data
provided corresponding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1951083U
Other languages
Japanese (ja)
Inventor
村上 元佑
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP1951083U priority Critical patent/JPS59130146U/en
Publication of JPS59130146U publication Critical patent/JPS59130146U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のメモリ装置のブロック図、第2図は従来
のメモリ装置を使用してマルチCPUシステムを構成し
た場合のブロック図、第3図は2つのCPLJからメモ
リ装置をアクセスされた場合の処理の仕方を示すタイミ
ングチャート、第4図は本考案のメモリ装置の概念図、
第5図は具体的実施例を示す図、第6図は二つのメモリ
の接続図である。 1・・・・・・メモリ、IA・・・・・・メモリーA、
IB・・・・・・メモリーB、2・・・・・・メモリア
ドレスレジスター、3・・・・・・メモリデータレジス
ター、4・・・・・・CPU又はcpt、tl、5・・
・・・・CPU2.6・・・・・・ゲート1.7・・・
・・・ゲート2.9・・・・・・メモリームアドレスレ
ジスター、10・・・・・・メモリーAデータレジスタ
ー、11・・・・・・メモリーBアドレスレジスター、
12・・・・・・メモリーBデータレジスター、13・
・・・・・メモリーA書込信号、14・・・・・・メモ
IJ−A読出し信号、15・・・・・・メモリーB書込
信号、16・・・・・・メモリーB読出し信号、17〜
24・・・・・・アンドゲート、25・・・・・・デー
タAの信号、26・・・・・・データAのNOT信号、
27・・・・・・データBの信号、28・・・・・・デ
ータBのNCjT信号。 −甲 ′u      Jh 第6図 /? 財
Figure 1 is a block diagram of a conventional memory device, Figure 2 is a block diagram of a multi-CPU system configured using conventional memory devices, and Figure 3 is a block diagram of a memory device accessed from two CPLJs. 4 is a conceptual diagram of the memory device of the present invention,
FIG. 5 is a diagram showing a specific embodiment, and FIG. 6 is a connection diagram of two memories. 1...Memory, IA...Memory A,
IB...Memory B, 2...Memory address register, 3...Memory data register, 4...CPU or cpt, tl, 5...
...CPU2.6...Gate 1.7...
...Gate 2.9...Memory address register, 10...Memory A data register, 11...Memory B address register,
12...Memory B data register, 13.
... Memory A write signal, 14 ... Memo IJ-A read signal, 15 ... Memory B write signal, 16 ... Memory B read signal, 17~
24...AND gate, 25...Data A signal, 26...Data A NOT signal,
27... Data B signal, 28... Data B NCjT signal. -K'u Jh Figure 6/? wealth

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 情報を記憶する複数のメモリと、各メモリに対応して設
けられメモリアドレスを置数するメモリアドレスレジス
タと、各メモリに対応して設けられメモリデータを置数
するメモリデータレジスタとを具備し、前記各メモリは
同一情報を記憶し各CPUよりアクセスされることを特
徴とするメモリ装置。
comprising a plurality of memories for storing information, a memory address register provided corresponding to each memory and storing a memory address, and a memory data register provided corresponding to each memory and storing memory data, A memory device characterized in that each of the memories stores the same information and is accessed by each CPU.
JP1951083U 1983-02-15 1983-02-15 memory device Pending JPS59130146U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1951083U JPS59130146U (en) 1983-02-15 1983-02-15 memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1951083U JPS59130146U (en) 1983-02-15 1983-02-15 memory device

Publications (1)

Publication Number Publication Date
JPS59130146U true JPS59130146U (en) 1984-09-01

Family

ID=30150654

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1951083U Pending JPS59130146U (en) 1983-02-15 1983-02-15 memory device

Country Status (1)

Country Link
JP (1) JPS59130146U (en)

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