JPH0272500U

JPH0272500U -

Info

Publication number: JPH0272500U
Application number: JP15026388U
Authority: JP
Priority date: 1988-11-17
Filing date: 1988-11-17
Publication date: 1990-06-01

Description

[Brief explanation of drawings]

図面は本考案のマイクロコンピユータのＲＡＭ
テスト回路を示す回路図である。１，２，３，４……入出力ポート、５……ＲＡ
Ｍ、６……選択ゲート、１１……データポインタ
、１３……１１ビツトカウンタ、１６……書き込
みデータ選択ゲート、２０……転送選択ゲート、
２３……読み出しデータ選択ゲート。 The drawing shows the RAM of the microcomputer of this invention.
FIG. 2 is a circuit diagram showing a test circuit. 1, 2, 3, 4...Input/output port, 5...RA
M, 6...Selection gate, 11...Data pointer, 13...11 bit counter, 16...Write data selection gate, 20...Transfer selection gate,
23...Read data selection gate.

Claims

[Claims for Utility Model Registration] (1) In a microcomputer with a built-in RAM in which data is stored, a data pointer that accesses the address of the RAM, a counter that performs a counting operation in synchronization with a system clock, and a test a selection gate that selects either the bit output of the data pointer or the bit output of the counter based on a signal, and accesses the address of the RAM by the selected output of the data pointer or the counter; an input/output port to which data to be written is applied to a predetermined address of the RAM and data read from a predetermined address of the RAM is output; when performing a data write/read test to the RAM; A RAM test circuit for a microcomputer, characterized in that the output of the counter is selected by the selection gate based on the test signal, and the address of the RAM is accessed by the output of the counter. (2) a transfer selection gate that selects whether or not to transfer data read from a predetermined address of the RAM to an internal bus based on the test signal; a read data selection gate that selects either read data of the RAM or data from the internal bus through the input/output port, and outputs the selected data from the RAM or the internal bus from the input/output port; a write data selection gate that selects either the write data applied to the input/output port or the data from the internal bus based on a signal, and causes the selected data to be written to a predetermined address of the RAM; When writing/reading data to the RAM, when writing data,
selecting write data applied to the input/output port by the write data selection gate;
A claim characterized in that, when reading data, a transfer selection gate prohibits the transfer of the read data of the RAM to the internal bus, and the read data selection gate selects the read data of the RAM. A RAM test circuit for a microcomputer described in item (1).