JPH0471174U - - Google Patents

Info

Publication number
JPH0471174U
JPH0471174U JP11473990U JP11473990U JPH0471174U JP H0471174 U JPH0471174 U JP H0471174U JP 11473990 U JP11473990 U JP 11473990U JP 11473990 U JP11473990 U JP 11473990U JP H0471174 U JPH0471174 U JP H0471174U
Authority
JP
Japan
Prior art keywords
data
channel
stored
display device
dma controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11473990U
Other languages
Japanese (ja)
Other versions
JP2555786Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990114739U priority Critical patent/JP2555786Y2/en
Publication of JPH0471174U publication Critical patent/JPH0471174U/ja
Application granted granted Critical
Publication of JP2555786Y2 publication Critical patent/JP2555786Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例の構成を示すブロツ
ク図。第２図は本考案の一実施例の作用の説明に
供するタイミング図。第３図は従来例の構成を示
すブロツク図。第４図は従来例の作用の説明に供
するタイミング図。 １……ＤＭＡコントローラ、２２１，２２，２
３および２４……データメモリ、３……メモリセ
レクタ、４……ＤＭＡフリツプフロツプ、５……
マルチポートメモリ、６……アドレス発生器、８
……ＣＰＵ。 FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a timing diagram for explaining the operation of one embodiment of the present invention. FIG. 3 is a block diagram showing the configuration of a conventional example. FIG. 4 is a timing chart for explaining the operation of the conventional example. 1...DMA controller, 22 1 , 2 2 , 2
3 and 2 4 ...data memory, 3...memory selector, 4...DMA flip-flop, 5...
Multiport memory, 6...Address generator, 8
...CPU.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 多チヤンネルの入力を有するデジタルオシロス
コープにおける多チヤンネルデータ同時転送表示
装置であつて、多チヤンネル分のデータを同時に
転送するＤＭＡコントローラと、ＤＭＡコントロ
ーラによつて転送された多チヤンネル分のデータ
をチヤンネル別に格納するデータメモリと、デー
タメモリに格納された記憶データを演算処理した
データが読み出し動作とは非同期で書き込まれて
演算処理されたデータを格納するマルチポートメ
モリとを備え、マルチポートメモリに格納された
記憶データをチヤンネル毎に読み出して読み出さ
れたデータの内容に伴う表示を行うことを特徴と
する多チヤンネルデータ同時転送表示装置。 A multi-channel data simultaneous transfer display device in a digital oscilloscope having multi-channel input, including a DMA controller that simultaneously transfers multi-channel data and storing multi-channel data transferred by the DMA controller for each channel. and a multi-port memory in which the data obtained by processing the stored data stored in the data memory is written asynchronously with the read operation, and the data is stored in the multi-port memory. A multi-channel data simultaneous transfer display device characterized by reading out stored data channel by channel and displaying information according to the contents of the read data.
JP1990114739U 1990-11-02 1990-11-02 Multi-channel data simultaneous transfer display device Expired - Fee Related JP2555786Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990114739U JP2555786Y2 (en) 1990-11-02 1990-11-02 Multi-channel data simultaneous transfer display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990114739U JP2555786Y2 (en) 1990-11-02 1990-11-02 Multi-channel data simultaneous transfer display device

Publications (2)

Publication Number Publication Date
JPH0471174U true JPH0471174U (en) 1992-06-24
JP2555786Y2 JP2555786Y2 (en) 1997-11-26

Family

ID=31862451

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990114739U Expired - Fee Related JP2555786Y2 (en) 1990-11-02 1990-11-02 Multi-channel data simultaneous transfer display device

Country Status (1)

Country Link
JP (1) JP2555786Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009122181A (en) * 2007-11-12 2009-06-04 Yamatake Corp Data processor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63108267A (en) * 1986-10-09 1988-05-13 テクトロニックス・インコーポレイテッド Waveform display unit
JPH021579A (en) * 1988-05-02 1990-01-05 Sony Tektronix Corp Memory device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63108267A (en) * 1986-10-09 1988-05-13 テクトロニックス・インコーポレイテッド Waveform display unit
JPH021579A (en) * 1988-05-02 1990-01-05 Sony Tektronix Corp Memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009122181A (en) * 2007-11-12 2009-06-04 Yamatake Corp Data processor

Also Published As

Publication number Publication date
JP2555786Y2 (en) 1997-11-26

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Legal Events

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LAPS Cancellation because of no payment of annual fees