JPS6431450U - - Google Patents
Info
- Publication number
- JPS6431450U JPS6431450U JP12377987U JP12377987U JPS6431450U JP S6431450 U JPS6431450 U JP S6431450U JP 12377987 U JP12377987 U JP 12377987U JP 12377987 U JP12377987 U JP 12377987U JP S6431450 U JPS6431450 U JP S6431450U
- Authority
- JP
- Japan
- Prior art keywords
- address
- memory
- data
- signal
- writing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012790 confirmation Methods 0.000 claims 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は本考案の一実施例に係る装置のブロツ
ク図、第２図は本考案の一実施例を示す説明図、
第３図は本考案の他の実施例を示すフローチヤー
トである。
１……ＣＰＵ、２……ＲＡＭ、３……アドレス
バス、４……内部レジスタ、５……ＲＯＭ。
FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an embodiment of the present invention,
FIG. 3 is a flowchart showing another embodiment of the present invention. 1...CPU, 2...RAM, 3...address bus, 4...internal register, 5...ROM.
Claims (1)
、 該メモリの個々の領域をアドレスするためのア
ドレス信号を転送する複数のアドレスバスと、 該複数のアドレスバスのうち、接続が確認され
るアドレスバスの信号論理を該アドレスバス以外
のアドレスバスの信号論理と異ならせたアドレス
信号を生成するアドレス信号生成手段と、 該アドレス信号生成手段によつて生成されたア
ドレス信号で前記メモリをアドレスすることによ
つて前記メモリにデータを書込む書込み手段と、 前記アドレス信号生成手段によつて生成された
アドレス信号で前記メモリをアドレスすることに
よつて前記メモリからデータを読出す読出し手段
と、 該読出し手段が読出したデータと前記書込み手
段が書込んだデータとを比較する比較手段と を具えたことを特徴とするアドレスバスの接続確
認装置。 (2) 実用新案登録請求の範囲第１項記載のアド
レスバスの接続確認装置において、前記読出し手
段は前記メモリ内の既存データを一時記憶する手
段を有することを特徴とするアドレスバスの接続
確認装置。[Claims for Utility Model Registration] (1) A memory in which data can be written/read, a plurality of address buses that transfer address signals for addressing individual areas of the memory, and a plurality of address buses that transfer address signals for addressing individual areas of the memory. Address signal generation means for generating an address signal in which the signal logic of an address bus whose connection is confirmed is different from the signal logic of address buses other than the address bus; and an address generated by the address signal generation means. writing means for writing data into said memory by addressing said memory with a signal; and writing means for writing data from said memory by addressing said memory with an address signal generated by said address signal generating means. 1. An address bus connection confirmation device comprising: reading means for reading; and comparison means for comparing data read by the reading means and data written by the writing means. (2) The address bus connection confirmation device according to claim 1, wherein the reading means has means for temporarily storing existing data in the memory. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12377987U JPS6431450U (en) | 1987-08-14 | 1987-08-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12377987U JPS6431450U (en) | 1987-08-14 | 1987-08-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6431450U true JPS6431450U (en) | 1989-02-27 |
Family
ID=31372943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12377987U Pending JPS6431450U (en) | 1987-08-14 | 1987-08-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6431450U (en) |
-
1987
- 1987-08-14 JP JP12377987U patent/JPS6431450U/ja active Pending
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