JPS6170243U - - Google Patents
Info
- Publication number
- JPS6170243U JPS6170243U JP15472184U JP15472184U JPS6170243U JP S6170243 U JPS6170243 U JP S6170243U JP 15472184 U JP15472184 U JP 15472184U JP 15472184 U JP15472184 U JP 15472184U JP S6170243 U JPS6170243 U JP S6170243U
- Authority
- JP
- Japan
- Prior art keywords
- parity
- data
- pair
- parity signal
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 claims description 13
- 230000004044 response Effects 0.000 claims 2
- 230000006870 function Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
図面は本発明の実施例を示すデータ書込読出装
置の回路図である。
１０，１１…データメモリ、１５…上位パリテ
イチエツカジエネレータ、１６…下位パリテイチ
エツカジエネレータ、１７…パリテイレジスタ、
２０…パリテイ信号メモリ、２１…チエツク信号
レジスタ、２２…制御信号発生回路。
The drawing is a circuit diagram of a data writing/reading device showing an embodiment of the present invention. 10, 11...data memory, 15...upper parity checker generator, 16...lower parity checker generator, 17...parity register,
20... Parity signal memory, 21... Check signal register, 22... Control signal generation circuit.
Claims (1)
位ビツト部に分割して記憶する一対のデータメモ
リを備え、データ書込時においては前記データを
２分し、それぞれ異なるタイミングで一対のデー
タメモリに順次書込むようにしたデータ書込装置
において、前記一対のデータメモリにそれぞれ接
続され書込まれるデータに応じたパリテイ信号を
発生する一対のパリテイジエネレータと、これら
一対のパリテイジエネレータの内、一方のパリテ
イジエネレータのパリテイ信号出力端子に接続さ
れたパリテイレジスタと、前記一対のパリテイジ
ユネレータの内他方のパリテイジエネレータのパ
リテイ信号出力端子に接続されこの他方のパリテ
イジエネレータのパリテイ出力を記憶するパリテ
イ信号メモリと、このパリテイ信号メモリから出
力されるパリテイ信号と前記一対のデータメモリ
から読出されるデータとに基づいてパリテイチエ
ツクを行うパリテイチエツカと、前記一対のデー
タメモリの内一方のデータメモリへのデータの書
込みに応答して前記一方のパリテイジエネレータ
から出力されるパリテイ信号を前記パリテイレジ
スタに記憶させ、他方のデータメモリへのデータ
の書込みに応答して前記パリテイレジスタに記憶
されたパリテイ信号を他方のパリテイジエネレー
タのパリテイ信号入力端子に供給するとともに、
この他方のパリテイジエネレータのパリテイ信号
出力を前記パリテイ信号メモリに書込み、前記一
対のデータメモリからデータを読出す場合には、
前記パリテイ信号メモリに記憶されたパリテイ信
号を前記パリテイチエツカのパリテイ信号入力端
子に供給する制御回路とを設けたことを特徴とす
るパリテイチエツク機能を備えた書込読出装置。 It is equipped with a pair of data memories that store data consisting of multiple bits divided into an upper bit part and a lower bit part, and when writing data, the data is divided into two parts and sequentially written to the pair of data memories at different timings. a pair of parity generators each connected to the pair of data memories and generating a parity signal according to the data to be written; and one of the pair of parity generators. a parity register connected to the parity signal output terminal of the parity generator of the pair; and a parity register connected to the parity signal output terminal of the other parity generator of the pair of parity generators. a parity signal memory for storing a parity output; a parity checker for performing a parity check based on a parity signal output from the parity signal memory and data read from the pair of data memories; A parity signal output from the one parity generator in response to data writing to one data memory is stored in the parity register, and the parity signal is stored in the parity register in response to data writing to the other data memory. Supplying the parity signal stored in the parity register to the parity signal input terminal of the other parity generator,
When writing the parity signal output of the other parity generator to the parity signal memory and reading data from the pair of data memories,
A read/write device having a parity check function, further comprising a control circuit for supplying a parity signal stored in the parity signal memory to a parity signal input terminal of the parity checker.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15472184U JPH0129639Y2 (en) | 1984-10-12 | 1984-10-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15472184U JPH0129639Y2 (en) | 1984-10-12 | 1984-10-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6170243U true JPS6170243U (en) | 1986-05-14 |
| JPH0129639Y2 JPH0129639Y2 (en) | 1989-09-08 |
Family
ID=30712712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15472184U Expired JPH0129639Y2 (en) | 1984-10-12 | 1984-10-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0129639Y2 (en) |
-
1984
- 1984-10-12 JP JP15472184U patent/JPH0129639Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0129639Y2 (en) | 1989-09-08 |
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