JPS603999U - LSI with built-in memory - Google Patents
LSI with built-in memoryInfo
- Publication number
- JPS603999U JPS603999U JP9735983U JP9735983U JPS603999U JP S603999 U JPS603999 U JP S603999U JP 9735983 U JP9735983 U JP 9735983U JP 9735983 U JP9735983 U JP 9735983U JP S603999 U JPS603999 U JP S603999U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- latch
- built
- lsi
- supplied
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Read Only Memory (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はゲートアレイにおけるメモリ周辺の回路構成を
示す図、第２図は本考案の実施例を示すブ冶ツク図であ
り、ゲートアレイ内部のメモリ周辺の構成のみを抽出し
て示す図、第３図は本考案実施例の動作を示すタイミン
グチャートである。
２１・・・メモリ本体、２２・・・書込みデータラッチ
、２３・・・書込みアドレスラッチ、２４・・・書込み
イネーブルラッチ。FIG. 1 is a diagram showing the circuit configuration around the memory in the gate array, FIG. 2 is a block diagram showing an embodiment of the present invention, and is a diagram showing only the configuration around the memory inside the gate array, FIG. 3 is a timing chart showing the operation of the embodiment of the present invention. 21...Memory body, 22...Write data latch, 23...Write address latch, 24...Write enable latch.
Claims (1)
はメモリ本体と、このメモリ本体に対し供給される書込
みデータを保持する第１のラッチと、上記メモリ本体に
対し供給される書込みアドレスを保持する第２のラッチ
と、上記メモリ本体に対し供給される書込みイネーブル
信号をラッチする第３のラッチで構成され、上記第１〜
第３のラッチに保持された出力を使用してデータ書込み
を行なうことを特徴とするメモリ内蔵ＬＳＩ０The LSI includes a memory and a combinational circuit, and the memory includes a memory body, a first latch that holds write data supplied to the memory body, and a write address supplied to the memory body. It is composed of a second latch and a third latch that latches a write enable signal supplied to the memory main body, and
Memory built-in LSI0 characterized by writing data using the output held in the third latch
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9735983U JPS603999U (en) | 1983-06-23 | 1983-06-23 | LSI with built-in memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9735983U JPS603999U (en) | 1983-06-23 | 1983-06-23 | LSI with built-in memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS603999U true JPS603999U (en) | 1985-01-12 |
Family
ID=30231620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9735983U Pending JPS603999U (en) | 1983-06-23 | 1983-06-23 | LSI with built-in memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS603999U (en) |
-
1983
- 1983-06-23 JP JP9735983U patent/JPS603999U/en active Pending
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