JPS617000U

JPS617000U - Built-in memory LSI

Info

Publication number: JPS617000U
Application number: JP8872684U
Authority: JP
Inventors: 清貴酒井
Original assignee: 日本電気株式会社
Priority date: 1984-06-14
Filing date: 1984-06-14
Publication date: 1986-01-16

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

図は本考案になるメモリ内蔵型ＬＳＩの一実施例の構造
を示すブロック図である。１・・・データ外部入力信号、２・・・データ内部入力
信号、３，４・・・試験端子入力、５・・・書込み制御
外部入力、６・・・書込み制御内部入力、７・・・アド
レス内部入力、訃・・メモリデータ外部出力、９・・・
メモリデータ内部出力、１０・・・アドレス専用カウン
タ出力、１１・・・メ舌リデータ入力、１２・・・メモ
リ書込み信号、１３・・・メモリアドレス信号、１６・
・・メモリデータ出力、２１〜２５・・・端子、１００
・・・メモリ内蔵型ＬＳＩ、１０１・・・メモリ入力信
号制御部、１０２・・・書込み信号制御部、１０３・・
・アドレス信号制御部、＝１０４・・・アドレス専用カ
ウンタ、１０６・・・メモリ出力信号制御部。The figure is a block diagram showing the structure of an embodiment of a memory built-in LSI according to the present invention. 1... Data external input signal, 2... Data internal input signal, 3, 4... Test terminal input, 5... Write control external input, 6... Write control internal input, 7... Address internal input, memory data external output, 9...
Memory data internal output, 10... Address dedicated counter output, 11... Memorized data input, 12... Memory write signal, 13... Memory address signal, 16.
...Memory data output, 21-25...terminal, 100
... Memory built-in LSI, 101 ... Memory input signal control section, 102 ... Write signal control section, 103 ...
-Address signal control section =104...Address dedicated counter, 106...Memory output signal control section.

Claims

[Scope of utility model registration request]

A built-in memory LSI0 having a configuration in which an address-only counter is provided inside the LSI, and means is further provided for supplying an address to the memory using the address-only counter when testing the memory built into the LSI.