JPS61199800U - - Google Patents

Info

Publication number
JPS61199800U
JPS61199800U JP8204385U JP8204385U JPS61199800U JP S61199800 U JPS61199800 U JP S61199800U JP 8204385 U JP8204385 U JP 8204385U JP 8204385 U JP8204385 U JP 8204385U JP S61199800 U JPS61199800 U JP S61199800U
Authority
JP
Japan
Prior art keywords
circuit
data
comparison
setting circuit
data setting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8204385U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8204385U priority Critical patent/JPS61199800U/ja
Publication of JPS61199800U publication Critical patent/JPS61199800U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のメモリ試験装置の実施例を示
すブロツク図。 1……発振回路、2……カウンタ回路、3……
データ設定回路、4……被試験素子、5……制御
回路、6……比較回路、7……表示回路。
FIG. 1 is a block diagram showing an embodiment of the memory testing device of the present invention. 1...Oscillation circuit, 2...Counter circuit, 3...
Data setting circuit, 4...Device under test, 5...Control circuit, 6...Comparison circuit, 7...Display circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] アドレスを指定するカウンタ回路と、検索すべ
きデータを設定するデータ設定回路と、このデー
タ設定回路に設定されたデータと被試験素子から
読み出されたデータとを比較し両者が不一致の場
合には不一致信号を出力する比較回路と不良を表
示する表示回路によつて構成されることを特徴と
するメモリ試験装置。
A counter circuit that specifies an address, a data setting circuit that sets the data to be searched, and a comparison between the data set in this data setting circuit and the data read from the device under test, and if the two do not match, A memory testing device comprising a comparison circuit that outputs a mismatch signal and a display circuit that displays a defect.
JP8204385U 1985-05-31 1985-05-31 Pending JPS61199800U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8204385U JPS61199800U (en) 1985-05-31 1985-05-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8204385U JPS61199800U (en) 1985-05-31 1985-05-31

Publications (1)

Publication Number Publication Date
JPS61199800U true JPS61199800U (en) 1986-12-13

Family

ID=30629402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8204385U Pending JPS61199800U (en) 1985-05-31 1985-05-31

Country Status (1)

Country Link
JP (1) JPS61199800U (en)

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