JPH0296700U - - Google Patents
Info
- Publication number
- JPH0296700U JPH0296700U JP258689U JP258689U JPH0296700U JP H0296700 U JPH0296700 U JP H0296700U JP 258689 U JP258689 U JP 258689U JP 258689 U JP258689 U JP 258689U JP H0296700 U JPH0296700 U JP H0296700U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- fail
- signal
- counter
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 101100444142 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) dut-1 gene Proteins 0.000 claims 1
- 230000002950 deficient Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第1図はこの考案による実施例の構成図、第2
図は第1図のメモリの説明図、第3図は従来技術
による構成図である。
1……DUT、2……フエイルメモリ、3……
Xメモリ、4……Yメモリ、5……Xカウンタ、
6……Yカウンタ。
Figure 1 is a configuration diagram of an embodiment according to this invention, Figure 2
The figure is an explanatory diagram of the memory shown in FIG. 1, and FIG. 3 is a configuration diagram according to the prior art. 1...DUT, 2...Fail memory, 3...
X memory, 4...Y memory, 5...X counter,
6...Y counter.
Claims (1)
2と、フエイルメモリ2の信号11とXアドレス
信号12を入力とするXメモリ3と、フエイルメ
モリ2の信号11とYアドレス信号13を入力と
するYメモリ4とをもつメモリICの不良表示回
路であつて、 Xメモリ3に接続されるXカウンタ5と、 Yメモリ4に接続されるYカウンタ6とを備え
ることを特徴とするメモリICの不良個所計数回
路。[Claims for Utility Model Registration] A fail memory 2 in which the fail of the DUT 1 is written, an X memory 3 to which the signal 11 of the fail memory 2 and the X address signal 12 are input, and a signal 11 of the fail memory 2 and the Y address signal 13 are input. A defective display circuit for a memory IC having a Y memory 4, characterized in that it comprises an X counter 5 connected to the X memory 3, and a Y counter 6 connected to the Y memory 4. Place counting circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP258689U JPH0296700U (en) | 1989-01-12 | 1989-01-12 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP258689U JPH0296700U (en) | 1989-01-12 | 1989-01-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0296700U true JPH0296700U (en) | 1990-08-01 |
Family
ID=31203481
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP258689U Pending JPH0296700U (en) | 1989-01-12 | 1989-01-12 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0296700U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008020238A (en) * | 2006-07-11 | 2008-01-31 | Yokogawa Electric Corp | Signal process device and tester for semiconductor integrated circuit |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5721000A (en) * | 1980-07-14 | 1982-02-03 | Nec Corp | Memory measuring device |
JPS62204500A (en) * | 1986-03-04 | 1987-09-09 | Mitsubishi Electric Corp | Testing instrument for memory ic with multioutput redundancy circuit |
-
1989
- 1989-01-12 JP JP258689U patent/JPH0296700U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5721000A (en) * | 1980-07-14 | 1982-02-03 | Nec Corp | Memory measuring device |
JPS62204500A (en) * | 1986-03-04 | 1987-09-09 | Mitsubishi Electric Corp | Testing instrument for memory ic with multioutput redundancy circuit |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008020238A (en) * | 2006-07-11 | 2008-01-31 | Yokogawa Electric Corp | Signal process device and tester for semiconductor integrated circuit |
JP4706577B2 (en) * | 2006-07-11 | 2011-06-22 | 横河電機株式会社 | Signal processing apparatus and semiconductor integrated circuit test apparatus |
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