JPS5721000A - Memory measuring device - Google Patents
Memory measuring deviceInfo
- Publication number
- JPS5721000A JPS5721000A JP9604980A JP9604980A JPS5721000A JP S5721000 A JPS5721000 A JP S5721000A JP 9604980 A JP9604980 A JP 9604980A JP 9604980 A JP9604980 A JP 9604980A JP S5721000 A JPS5721000 A JP S5721000A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- fbm101
- pattern generator
- outputted
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
Landscapes
- Tests Of Electronic Circuits (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Semiconductor Integrated Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
PURPOSE:To discriminate at a high speed whether a memory to be measured is normal or not, by counting the number of defective bits accurately. CONSTITUTION:Address information 103 and input data information 104 outputted from a pattern generator 102 are supplied to an FBM101 and a memory 106 to be measured to compare the output 107 of the memory 106 with expected data 105 outputted from the pattern generator and when the both do not coincide with each other, a fail signal 109 is generated to write a 1 in an error address of the FBM101. After the completion of a test, a counter 301 is set to a 0 and addresses are generated and supplied by the pattern generator to the FBM101 successively; after the FBM is read within a prescribed range, the contents of the counter 301 and read to know the number of defective bits.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9604980A JPS5721000A (en) | 1980-07-14 | 1980-07-14 | Memory measuring device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9604980A JPS5721000A (en) | 1980-07-14 | 1980-07-14 | Memory measuring device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5721000A true JPS5721000A (en) | 1982-02-03 |
Family
ID=14154602
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9604980A Pending JPS5721000A (en) | 1980-07-14 | 1980-07-14 | Memory measuring device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5721000A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63127499A (en) * | 1986-11-17 | 1988-05-31 | Yamada Denon Kk | Device for inspecting memory element |
JPS6414797A (en) * | 1987-07-08 | 1989-01-18 | Nec Corp | Semiconductor integrated memory |
EP0347970A2 (en) * | 1988-06-18 | 1989-12-27 | Philips Patentverwaltung GmbH | Read-only memory test method, and device for carrying out the method |
JPH0296700U (en) * | 1989-01-12 | 1990-08-01 |
-
1980
- 1980-07-14 JP JP9604980A patent/JPS5721000A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63127499A (en) * | 1986-11-17 | 1988-05-31 | Yamada Denon Kk | Device for inspecting memory element |
JPS6414797A (en) * | 1987-07-08 | 1989-01-18 | Nec Corp | Semiconductor integrated memory |
EP0347970A2 (en) * | 1988-06-18 | 1989-12-27 | Philips Patentverwaltung GmbH | Read-only memory test method, and device for carrying out the method |
JPH0296700U (en) * | 1989-01-12 | 1990-08-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4965799A (en) | Method and apparatus for testing integrated circuit memories | |
DE59101394D1 (en) | INTEGRATED SEMICONDUCTOR MEMORY WITH PARALLEL TEST POSSIBILITY AND REDUNDANCY PROCESS. | |
EP0291283A3 (en) | Memory test method and apparatus | |
JPS5721000A (en) | Memory measuring device | |
KR970017693A (en) | Test circuit | |
EP0220577B1 (en) | Memory array | |
JPS573298A (en) | Memory integrated circuit | |
JPS55163697A (en) | Memory device | |
ES451528A1 (en) | Method of and arrangement for detecting faults in a memory device | |
KR920003159A (en) | Fast Testing of Programmable Logic Devices | |
KR880004490A (en) | Semiconductor memory | |
JPS56169292A (en) | Storage device | |
JP2620072B2 (en) | Logic circuit test equipment | |
JPS5694598A (en) | Memory error correction control system | |
JPS5673363A (en) | Testing device of ic | |
JPS5320823A (en) | Memory unit test system | |
JPS5683900A (en) | Buffer recording device | |
JPS5693193A (en) | Ic memory test device | |
JPS5798197A (en) | Multiplexing memory device | |
JPS5587396A (en) | Memory test system | |
SU1040526A1 (en) | Memory having self-check | |
JPS5534380A (en) | Fail memory | |
JPS60136998A (en) | Semiconductor storage device | |
JPS5744296A (en) | Storage device | |
JPH02271273A (en) | Lsi evaluation apparatus |