JPS5534380A - Fail memory - Google Patents

Fail memory

Info

Publication number
JPS5534380A
JPS5534380A JP10837478A JP10837478A JPS5534380A JP S5534380 A JPS5534380 A JP S5534380A JP 10837478 A JP10837478 A JP 10837478A JP 10837478 A JP10837478 A JP 10837478A JP S5534380 A JPS5534380 A JP S5534380A
Authority
JP
Japan
Prior art keywords
fail
memory
comparator
fai
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10837478A
Other languages
Japanese (ja)
Other versions
JPS5838879B2 (en
Inventor
Naoaki Narumi
Takako Maekawa
Koji Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP53108374A priority Critical patent/JPS5838879B2/en
Publication of JPS5534380A publication Critical patent/JPS5534380A/en
Publication of JPS5838879B2 publication Critical patent/JPS5838879B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to know the quality of a tested circuit corresponding to bits by counting the number of defective bits in real time while writing the defective bits to a fail memory in execution of a test.
CONSTITUTION: At every time when a comparator detects "Fai l" in execution of a test, information at input terminal DIN of memory part 41 is written to a corresponding address and an address position where "Fai l" is not detected is held in a clear state. Gate part 42 makes fail information in memory 41 read out in the 1st half of the operation cycle of the fail memory into a gate control signal; when the content indicates a fail, the output signal from a comparator to counter part 43 is cut off and when the content is in the clear state, the output signal to counter part 43 is allowed. Counter part 43 counts only output signals discriminated as fail signals among output signals of the comparator inputted via gate part 42.
COPYRIGHT: (C)1980,JPO&Japio
JP53108374A 1978-09-04 1978-09-04 fail memory Expired JPS5838879B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53108374A JPS5838879B2 (en) 1978-09-04 1978-09-04 fail memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53108374A JPS5838879B2 (en) 1978-09-04 1978-09-04 fail memory

Publications (2)

Publication Number Publication Date
JPS5534380A true JPS5534380A (en) 1980-03-10
JPS5838879B2 JPS5838879B2 (en) 1983-08-25

Family

ID=14483143

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53108374A Expired JPS5838879B2 (en) 1978-09-04 1978-09-04 fail memory

Country Status (1)

Country Link
JP (1) JPS5838879B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5317573A (en) * 1989-08-30 1994-05-31 International Business Machines Corporation Apparatus and method for real time data error capture and compression redundancy analysis
WO1998014954A1 (en) * 1996-09-30 1998-04-09 Advantest Corporation Memory tester

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6268943A (en) * 1985-09-19 1987-03-30 荻原　岳彦 Water channel constituting member and molding frame apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5317573A (en) * 1989-08-30 1994-05-31 International Business Machines Corporation Apparatus and method for real time data error capture and compression redundancy analysis
WO1998014954A1 (en) * 1996-09-30 1998-04-09 Advantest Corporation Memory tester

Also Published As

Publication number Publication date
JPS5838879B2 (en) 1983-08-25

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