JPS5558896A - Analyzer for memory defect - Google Patents

Analyzer for memory defect

Info

Publication number
JPS5558896A
JPS5558896A JP13073478A JP13073478A JPS5558896A JP S5558896 A JPS5558896 A JP S5558896A JP 13073478 A JP13073478 A JP 13073478A JP 13073478 A JP13073478 A JP 13073478A JP S5558896 A JPS5558896 A JP S5558896A
Authority
JP
Japan
Prior art keywords
memory
signal
defective
address signals
recording
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13073478A
Other languages
Japanese (ja)
Inventor
Ichiro Midorikawa
Masato Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13073478A priority Critical patent/JPS5558896A/en
Publication of JPS5558896A publication Critical patent/JPS5558896A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make easy and ensure the analysis for defective memory, by writing the result of test on the recording memory through blocked memory to be tested.
CONSTITUTION: The memory cell in matrix connection of tested memory 1 is split into four sets of blocks B1WB4. The output read out from the blocks B1WB4 selected sequentially with the address signal A0... and the set output are detected, and the defective bit detection circuit 17 produces the signal such as high level in case of failure. The multiplexers 11W14 fed with the address signals A0, A1... with this propriety signal produce the address signals A16WA12 formed with the upper 4-bit of the address signals A0, A1..., select the memory cell for RAM 16 for recording, and if defective signal is written in once, the defective signal is kept in the cell. When the recording of the result of test for the bolck B1 is finished, the address signals A16WA12 are advanced, and the result of test of the block B2 is recorded similarly. This is the same to the remaining blocks B3, B4 and the analysis of defect of memory can easily and surely be made.
COPYRIGHT: (C)1980,JPO&Japio
JP13073478A 1978-10-24 1978-10-24 Analyzer for memory defect Pending JPS5558896A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13073478A JPS5558896A (en) 1978-10-24 1978-10-24 Analyzer for memory defect

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13073478A JPS5558896A (en) 1978-10-24 1978-10-24 Analyzer for memory defect

Publications (1)

Publication Number Publication Date
JPS5558896A true JPS5558896A (en) 1980-05-01

Family

ID=15041344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13073478A Pending JPS5558896A (en) 1978-10-24 1978-10-24 Analyzer for memory defect

Country Status (1)

Country Link
JP (1) JPS5558896A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5562598A (en) * 1978-10-31 1980-05-12 Nec Corp Memory check unit
JPS57130295A (en) * 1981-02-03 1982-08-12 Nec Corp Inspecting device for ic memory
JPS61283099A (en) * 1985-06-07 1986-12-13 Hitachi Electronics Eng Co Ltd Memory inspecting data recording system
JPH04177700A (en) * 1990-11-13 1992-06-24 Toshiba Corp Memory fault analysis device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5369546A (en) * 1976-12-03 1978-06-21 Fujitsu Ltd Method and apparatus for memory unit test
JPS54152929A (en) * 1978-05-24 1979-12-01 Fujitsu Ltd Fail category bit map display system of lsi memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5369546A (en) * 1976-12-03 1978-06-21 Fujitsu Ltd Method and apparatus for memory unit test
JPS54152929A (en) * 1978-05-24 1979-12-01 Fujitsu Ltd Fail category bit map display system of lsi memory

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5562598A (en) * 1978-10-31 1980-05-12 Nec Corp Memory check unit
JPS57130295A (en) * 1981-02-03 1982-08-12 Nec Corp Inspecting device for ic memory
JPS6220640B2 (en) * 1981-02-03 1987-05-08 Nippon Electric Co
JPS61283099A (en) * 1985-06-07 1986-12-13 Hitachi Electronics Eng Co Ltd Memory inspecting data recording system
JPH04177700A (en) * 1990-11-13 1992-06-24 Toshiba Corp Memory fault analysis device

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