JPS54148471A - Preset counter - Google Patents
Preset counterInfo
- Publication number
- JPS54148471A JPS54148471A JP5659078A JP5659078A JPS54148471A JP S54148471 A JPS54148471 A JP S54148471A JP 5659078 A JP5659078 A JP 5659078A JP 5659078 A JP5659078 A JP 5659078A JP S54148471 A JPS54148471 A JP S54148471A
- Authority
- JP
- Japan
- Prior art keywords
- count
- central processor
- counter
- register
- sent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
Landscapes
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To secure the count value setting, the counting command and the count- up detection for the counter through the program even with the central processor which has no numerical operation function by adding the 1-bit data transfer function to the central processor. CONSTITUTION:The count set value is sent out by one bit and in the form of the output data from the central processor via line l1 and then made to correspond to the address signals obtained through line l3 to be written in sequence into LR1- LR16 of ratch register 9 selected at selector circuit 11. Then the counting command ''1'' sent from l1 is written into LR17 of register 9, and this output releases the reset of counter 2 and count-up memory circuit 5. At the same time, the input pulse sent from the processor is applied to counter 2 via level changer 1. After this, the count value is compared with the set value of LR1-LR16 of register 9 through coincidence detector 3, and memory circuit 5 is set when a coincidence is obtained in the comparison. Thus, the fact of count-up is read at all times through the central processor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5659078A JPS54148471A (en) | 1978-05-15 | 1978-05-15 | Preset counter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5659078A JPS54148471A (en) | 1978-05-15 | 1978-05-15 | Preset counter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54148471A true JPS54148471A (en) | 1979-11-20 |
Family
ID=13031394
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5659078A Pending JPS54148471A (en) | 1978-05-15 | 1978-05-15 | Preset counter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54148471A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57106239A (en) * | 1980-12-24 | 1982-07-02 | Canon Inc | Oscillating circuit |
-
1978
- 1978-05-15 JP JP5659078A patent/JPS54148471A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57106239A (en) * | 1980-12-24 | 1982-07-02 | Canon Inc | Oscillating circuit |
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