JPS5452946A - Semiconductor element - Google Patents

Semiconductor element

Info

Publication number
JPS5452946A
JPS5452946A JP11901777A JP11901777A JPS5452946A JP S5452946 A JPS5452946 A JP S5452946A JP 11901777 A JP11901777 A JP 11901777A JP 11901777 A JP11901777 A JP 11901777A JP S5452946 A JPS5452946 A JP S5452946A
Authority
JP
Japan
Prior art keywords
test
signal
supplied
expected value
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11901777A
Other languages
Japanese (ja)
Other versions
JPS6039186B2 (en
Inventor
Yoshimitsu Takiguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP52119017A priority Critical patent/JPS6039186B2/ja
Publication of JPS5452946A publication Critical patent/JPS5452946A/en
Publication of JPS6039186B2 publication Critical patent/JPS6039186B2/ja
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To secure easy formation of the test data in case the test is carried out by giving the test data to the tested logic circuit, by increasing the point where the actual action is compared with the expected value.
CONSTITUTION: Both the control signal and the writing signal for the test action are supplied to terminal 105 and 104, and the signal counting the address is applied to terminal 103. Thus, the test input data or expected value 101 and 102 are written into memory element 4. In the case of the actual test, the reading signal is supplied to 104 and the control signal for the test action is supplied to 105 respectively, and the signal to count the address is supplied to 103. As a result, the test input data of the expected value is read out from element 4 to be supplied to control circuit 5. Circuit 5 applies the test input data to logic A and the expected value to comparator 6 respectively. Circuit 6 compares the expected value with the logic value of the actual action with every point. And when no coincidence is obtained, the disagreement signal is delivered to pin 203
COPYRIGHT: (C)1979,JPO&Japio
JP52119017A 1977-10-05 1977-10-05 Expired JPS6039186B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52119017A JPS6039186B2 (en) 1977-10-05 1977-10-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52119017A JPS6039186B2 (en) 1977-10-05 1977-10-05

Publications (2)

Publication Number Publication Date
JPS5452946A true JPS5452946A (en) 1979-04-25
JPS6039186B2 JPS6039186B2 (en) 1985-09-04

Family

ID=14750915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52119017A Expired JPS6039186B2 (en) 1977-10-05 1977-10-05

Country Status (1)

Country Link
JP (1) JPS6039186B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57192062A (en) * 1981-05-22 1982-11-26 Hitachi Ltd Semiconductor integrated circuit device
JPS61128180A (en) * 1984-11-20 1986-06-16 Texas Instruments Inc Self-testing equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57192062A (en) * 1981-05-22 1982-11-26 Hitachi Ltd Semiconductor integrated circuit device
JPS61128180A (en) * 1984-11-20 1986-06-16 Texas Instruments Inc Self-testing equipment

Also Published As

Publication number Publication date
JPS6039186B2 (en) 1985-09-04

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