JPS5557905A - Program controller - Google Patents

Program controller

Info

Publication number
JPS5557905A
JPS5557905A JP13080578A JP13080578A JPS5557905A JP S5557905 A JPS5557905 A JP S5557905A JP 13080578 A JP13080578 A JP 13080578A JP 13080578 A JP13080578 A JP 13080578A JP S5557905 A JPS5557905 A JP S5557905A
Authority
JP
Japan
Prior art keywords
output
signal
memory
input
outputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13080578A
Other languages
Japanese (ja)
Other versions
JPS6115445B2 (en
Inventor
Tadao Totsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP13080578A priority Critical patent/JPS5557905A/en
Publication of JPS5557905A publication Critical patent/JPS5557905A/en
Publication of JPS6115445B2 publication Critical patent/JPS6115445B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Executing Machine-Instructions (AREA)
  • Control By Computers (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE: To perform definite control by a simple constitution and also to write program control conditions easily by holding an input-output condition signal in a memory corresponding to the output of a comparator generated at the time of variation of a control result signal.
CONSTITUTION: As the output signal of a limit switch, control result signal S of "1" is outputted from 1st input selector 3 and S is compared 10 with input condition signal RIN outputted from memory 5; and S and PIN become "1" and "0" respectively and "1" is outputted from output terminal OUT1. In the next cycle, S of "1" is written as PIN in memory 5. On the other hand, the signal of "1" from OUT1 makes step counter 11 count up by one through AND gate 14 to address to the 2nd step. Therefore, input and output conditions written at the 1st step position of memory 5 are left unchanged as they are and the writing operation of the 1st step ends.
COPYRIGHT: (C)1980,JPO&Japio
JP13080578A 1978-10-24 1978-10-24 Program controller Granted JPS5557905A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13080578A JPS5557905A (en) 1978-10-24 1978-10-24 Program controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13080578A JPS5557905A (en) 1978-10-24 1978-10-24 Program controller

Publications (2)

Publication Number Publication Date
JPS5557905A true JPS5557905A (en) 1980-04-30
JPS6115445B2 JPS6115445B2 (en) 1986-04-24

Family

ID=15043115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13080578A Granted JPS5557905A (en) 1978-10-24 1978-10-24 Program controller

Country Status (1)

Country Link
JP (1) JPS5557905A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62121506A (en) * 1985-11-22 1987-06-02 Kikuchi Goro Direct teaching reproducing type sequence controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62121506A (en) * 1985-11-22 1987-06-02 Kikuchi Goro Direct teaching reproducing type sequence controller

Also Published As

Publication number Publication date
JPS6115445B2 (en) 1986-04-24

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