JPS5523565A - Instruction extension system of computer - Google Patents
Instruction extension system of computerInfo
- Publication number
- JPS5523565A JPS5523565A JP9618078A JP9618078A JPS5523565A JP S5523565 A JPS5523565 A JP S5523565A JP 9618078 A JP9618078 A JP 9618078A JP 9618078 A JP9618078 A JP 9618078A JP S5523565 A JPS5523565 A JP S5523565A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- signal
- address
- decoders
- inputted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To make a processing high-speed by defining a firmware instruction and a basic instruction as a single instruction as the whole and making them into a micro program and processing them in a hardware level.
CONSTITUTION: The program from a main memory is inputted to register 21. Signal 9b of the instruction code field is inputted to decoders 22 and 26. In case of an extended instruction, signal 9c of the extending instruction code field is inputted to one of decoders 27 to 29. In the MJ (multiple jump) signal outputting time, gate 48 is opened to output the signal to ROM address register RAR. Then, the elementary operation EO address is proccessed as a basic instruction to perform multiple jump to the EO address. After that, when FF 46 is set by the MJ signal, it is indicated that this instruction is an extended instruction. Next, when the MJ signal is issued, outputs of decoders 27 to 29 are sent to RAR as the EO address through gate 49. Thus, the processing can be performed with a unified hardware.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9618078A JPS5523565A (en) | 1978-08-09 | 1978-08-09 | Instruction extension system of computer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9618078A JPS5523565A (en) | 1978-08-09 | 1978-08-09 | Instruction extension system of computer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5523565A true JPS5523565A (en) | 1980-02-20 |
Family
ID=14158113
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9618078A Pending JPS5523565A (en) | 1978-08-09 | 1978-08-09 | Instruction extension system of computer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5523565A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5878232A (en) * | 1981-11-04 | 1983-05-11 | Hitachi Ltd | Microprogram controlling data processing device |
WO1985002277A1 (en) * | 1983-11-11 | 1985-05-23 | Fujitsu Limited | Microprogram control method |
-
1978
- 1978-08-09 JP JP9618078A patent/JPS5523565A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5878232A (en) * | 1981-11-04 | 1983-05-11 | Hitachi Ltd | Microprogram controlling data processing device |
JPH0115092B2 (en) * | 1981-11-04 | 1989-03-15 | Hitachi Ltd | |
WO1985002277A1 (en) * | 1983-11-11 | 1985-05-23 | Fujitsu Limited | Microprogram control method |
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