JPS55164942A - Division circuit - Google Patents

Division circuit

Info

Publication number
JPS55164942A
JPS55164942A JP7319079A JP7319079A JPS55164942A JP S55164942 A JPS55164942 A JP S55164942A JP 7319079 A JP7319079 A JP 7319079A JP 7319079 A JP7319079 A JP 7319079A JP S55164942 A JPS55164942 A JP S55164942A
Authority
JP
Japan
Prior art keywords
register
circuit
dividend
input
fed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7319079A
Other languages
Japanese (ja)
Inventor
Toshio Tsuchiya
Katsumi Mori
Shinichi Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP7319079A priority Critical patent/JPS55164942A/en
Publication of JPS55164942A publication Critical patent/JPS55164942A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To speed up the operation and to make small the size of division circuit, by performing the operation of n bits by n-times clock and limiting the division of an integer in several-bits.
CONSTITUTION: Dividend (a) is input to the A register 1 and the divider (b) is to the B register 2, so that 2n,b, 2n-1,b...20,b can be input respectively to the gate groups 3nW30 connected to the register 2. The gate groups 3nW30 are sequentially open in the order of input for output, they are respectively compared with the dividend (a) in the register 1, and when a ≥2n,b, 2n-1,b...20,b is established, 1 is set to the shift register 6 with the output of the circuit 4, and the subtraction circuit 5 is operated to execute the respective operations and the results are fed to the register 1. On the other hand, in case of n<2n,b, 2n-1,b...20,b, 0 is set to the register 6, the dividend (a) is fed again to the register 1 via the circuit 5 as it is, this operation is repeated each digit, quotinents Pn, Pn-1...P0 are set to the register 6, and residual is fed to the register 1.
COPYRIGHT: (C)1980,JPO&Japio
JP7319079A 1979-06-11 1979-06-11 Division circuit Pending JPS55164942A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7319079A JPS55164942A (en) 1979-06-11 1979-06-11 Division circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7319079A JPS55164942A (en) 1979-06-11 1979-06-11 Division circuit

Publications (1)

Publication Number Publication Date
JPS55164942A true JPS55164942A (en) 1980-12-23

Family

ID=13510965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7319079A Pending JPS55164942A (en) 1979-06-11 1979-06-11 Division circuit

Country Status (1)

Country Link
JP (1) JPS55164942A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57161052U (en) * 1981-03-31 1982-10-09
JPS5833753A (en) * 1981-08-24 1983-02-28 Fujitsu Ltd Divider
JPS5972541A (en) * 1982-10-19 1984-04-24 Nec Corp Data processor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57161052U (en) * 1981-03-31 1982-10-09
JPS5833753A (en) * 1981-08-24 1983-02-28 Fujitsu Ltd Divider
JPS5972541A (en) * 1982-10-19 1984-04-24 Nec Corp Data processor

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