JPS5694435A - Multiplying circuit - Google Patents

Multiplying circuit

Info

Publication number
JPS5694435A
JPS5694435A JP17336279A JP17336279A JPS5694435A JP S5694435 A JPS5694435 A JP S5694435A JP 17336279 A JP17336279 A JP 17336279A JP 17336279 A JP17336279 A JP 17336279A JP S5694435 A JPS5694435 A JP S5694435A
Authority
JP
Japan
Prior art keywords
circuit
output
latches
input
stages
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17336279A
Other languages
Japanese (ja)
Inventor
Koichi Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17336279A priority Critical patent/JPS5694435A/en
Publication of JPS5694435A publication Critical patent/JPS5694435A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make the multiplication speed high, by providing the first and the second circuits in the multiplying circuit and by providing a latch group where intermediate data obtained in the course of addition of the input of the second circuit is held and by reducing the number of stages of latches.
CONSTITUTION: Multiplicand CAND and partial multiplier IER are input to output the product from circuit 1, and the output of circuit 1 is applied to circuit 10 where six inputs are added to output the addition result as four partial results. Further, four outputs of from circuit 10 are set to latches 11W14 as the sum of temporary carry, and contents of latches 11W14 are input to circuit 15 where four inputs are added to output the addition result as two partial results. The output of circuit 15 is shifted by a fixed quantity and is input to circuit 10, and circuits 10 and 15 are connected, and thus, the number of stages of latches is reduced to make the multiplication speed high.
COPYRIGHT: (C)1981,JPO&Japio
JP17336279A 1979-12-27 1979-12-27 Multiplying circuit Pending JPS5694435A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17336279A JPS5694435A (en) 1979-12-27 1979-12-27 Multiplying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17336279A JPS5694435A (en) 1979-12-27 1979-12-27 Multiplying circuit

Publications (1)

Publication Number Publication Date
JPS5694435A true JPS5694435A (en) 1981-07-30

Family

ID=15958990

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17336279A Pending JPS5694435A (en) 1979-12-27 1979-12-27 Multiplying circuit

Country Status (1)

Country Link
JP (1) JPS5694435A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59205646A (en) * 1983-05-09 1984-11-21 Matsushita Electric Ind Co Ltd Cumulative multiplier
JP2010249437A (en) * 2009-04-17 2010-11-04 Teruo Iejima Solar water heater
RU2473955C1 (en) * 2011-06-08 2013-01-27 Лев Петрович Петренко METHOD OF GENERATING ARGUMENTS OF ANALOGUE SIGNALS OF PARTIAL PRODUCTS [ni]&[mj]f(h)↓CD OF ARGUMENTS OF MULTIPLIERS ±[mj]f(2n) И ±[ni]f(2n) - "COMPLEMENTARY CODE" IN PYRAMIDAL MULTIPLIER fΣ(↓CDΣ) FOR SUCCESSIVE LOGIC DECRYPTION f1(CD↓) AND GENERATING RESULTANT SUM IN FORMAT ±[SΣ]f(2n) - "COMPLEMENTARY CODE" AND FUNCTIONAL STRUCTURE FOR REALISATION THEREOF (VERSIONS OF RUSSIAN LOGIC)
RU2475813C2 (en) * 2011-04-01 2013-02-20 Лев Петрович Петренко METHOD FOR LOGIC-DYNAMIC PROCESS OF GENERATING ANALOGUE INFORMATION SIGNALS OF PARTIAL PRODUCTS OF ARGUMENTS OF MULTIPLIERS ±[ni] AND ±[mj] - "COMPLEMENTARY CODE" OF TRUNCATED PYRAMIDAL STRUCTURE OF MULTIPLIER fΣ(Σ) FOR SUBSEQUENT ACCUMULATIVE SUMMATION IN ADDER ±f1(Σ) AND FUNCTIONAL DESIGN FOR REALISATION THEREOF (VERSIONS OF RUSSIAN LOGIC)
RU2481614C2 (en) * 2011-06-08 2013-05-10 Лев Петрович Петренко METHOD TO GENERATE ARGUMENTS OF ANALOG SIGNALS OF PARTIAL PRODUCTS [ni]&[mj]f(h)↓CD ARGUMENTS OF MULTIPLICAND ±[mj]f(2n) AND ARGUMENTS OF MULTIPLIER ±[ni]f(2n) - "ADDITIONAL CODE" IN PYRAMIDAL MULTIPLIER fΣ(↓CDΣ) FOR SUBSEQUENT LOGICAL DECODING f1(CD↓) AND GENERATION OF RESULTING SUM IN FORMAT ±[SΣ]f(2n) -"ADDITIONAL CODE" AND FUNCTIONAL STRUCTURE FOR ITS REALISATION (VERSIONS OF RUSSIAN LOGICS)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59205646A (en) * 1983-05-09 1984-11-21 Matsushita Electric Ind Co Ltd Cumulative multiplier
JPH0447850B2 (en) * 1983-05-09 1992-08-05 Matsushita Electric Ind Co Ltd
JP2010249437A (en) * 2009-04-17 2010-11-04 Teruo Iejima Solar water heater
RU2475813C2 (en) * 2011-04-01 2013-02-20 Лев Петрович Петренко METHOD FOR LOGIC-DYNAMIC PROCESS OF GENERATING ANALOGUE INFORMATION SIGNALS OF PARTIAL PRODUCTS OF ARGUMENTS OF MULTIPLIERS ±[ni] AND ±[mj] - "COMPLEMENTARY CODE" OF TRUNCATED PYRAMIDAL STRUCTURE OF MULTIPLIER fΣ(Σ) FOR SUBSEQUENT ACCUMULATIVE SUMMATION IN ADDER ±f1(Σ) AND FUNCTIONAL DESIGN FOR REALISATION THEREOF (VERSIONS OF RUSSIAN LOGIC)
RU2473955C1 (en) * 2011-06-08 2013-01-27 Лев Петрович Петренко METHOD OF GENERATING ARGUMENTS OF ANALOGUE SIGNALS OF PARTIAL PRODUCTS [ni]&[mj]f(h)↓CD OF ARGUMENTS OF MULTIPLIERS ±[mj]f(2n) И ±[ni]f(2n) - "COMPLEMENTARY CODE" IN PYRAMIDAL MULTIPLIER fΣ(↓CDΣ) FOR SUCCESSIVE LOGIC DECRYPTION f1(CD↓) AND GENERATING RESULTANT SUM IN FORMAT ±[SΣ]f(2n) - "COMPLEMENTARY CODE" AND FUNCTIONAL STRUCTURE FOR REALISATION THEREOF (VERSIONS OF RUSSIAN LOGIC)
RU2481614C2 (en) * 2011-06-08 2013-05-10 Лев Петрович Петренко METHOD TO GENERATE ARGUMENTS OF ANALOG SIGNALS OF PARTIAL PRODUCTS [ni]&[mj]f(h)↓CD ARGUMENTS OF MULTIPLICAND ±[mj]f(2n) AND ARGUMENTS OF MULTIPLIER ±[ni]f(2n) - "ADDITIONAL CODE" IN PYRAMIDAL MULTIPLIER fΣ(↓CDΣ) FOR SUBSEQUENT LOGICAL DECODING f1(CD↓) AND GENERATION OF RESULTING SUM IN FORMAT ±[SΣ]f(2n) -"ADDITIONAL CODE" AND FUNCTIONAL STRUCTURE FOR ITS REALISATION (VERSIONS OF RUSSIAN LOGICS)

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